BXT7059 / BXTS7059 7059-xxx No. 87-0067062-000 Revision C BIOS SETUP TECHNICAL REFERENCE Aptio® 4.
WARRANTY The following is an abbreviated version of Trenton Systems’ warranty policy for PICMG 1.3 products. For a complete warranty statement, contact Trenton or visit our website at www.TrentonSystems.com. Trenton PICMG 1.3 products are warranted against material and manufacturing defects for five years from date of delivery to the original purchaser. Buyer agrees that if this product proves defective Trenton Systems, Inc.
TRADEMARKS IBM, PC/AT, VGA, EGA, OS/2 and PS/2 are trademarks or registered trademarks of International Business Machines Corp. AMI, Aptio and AMIBIOS are trademarks of American Megatrends Inc. Intel, Xeon, Intel Quick Path Interconnect, Intel Hyper-Threading Technology and Intel Virtualization Technology are trademarks or registered trademarks of Intel Corporation. MS-DOS and Microsoft are registered trademarks of Microsoft Corp.
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Table of Contents CHAPTER 1 STARTING APTIO® TSE ................................................................................................ 1-1 Introduction ................................................................................................................................................... 1-1 Starting Aptio TSE ........................................................................................................................................ 1-1 Press DEL or F2 to enter Setup......
BXT7059 / BXTS7059 Technical Reference View SMBIOS Event Log...............................................................................................................................A-1 APPENDIX A BIOS MESSAGES ........................................................................................................... A-1 Introduction ...................................................................................................................................................
BXT7059 / BXTS7059 Technical Reference SHB HANDLING PRECAUTIONS WARNING: This product has components that may be damaged by electrostatic discharge. To protect your system host board (SHB) from electrostatic damage, be sure to observe the following precautions when handling or storing the board: Keep the SHB in its static-shielded bag until you are ready to perform your installation. Handle the SHB by its edges. Do not touch the I/O connector pins.
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BXT7059 / BXTS7059 Technical Reference Starting Aptio® TSE Chapter 1 Starting Aptio® TSE Introduction The BXT7059 and BXTS7059 feature the Aptio® 4.x BIOS from American Megatrends, Inc. (AMI) with a ROM-resident setup utility called the Aptio® Text Setup Environment or TSE.
Starting Aptio® TSE BXT7059 / BXTS7059 Technical Reference Aptio® TSE Setup Menu The Aptio TSE BIOS setup menu is the first screen that you can navigate. Each BIOS setup menu option is described in this user’s guide. Aptio Setup Utility – Copyright © 2013 American Megatrends Inc. Main Advanced BIOS Information BIOS Vendor Core Version Compliancy Project Version Build Date & Time Chipset Boot Security American Megatrends 4.6.5.4 UEFI 2.3.1; PI 1.
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BXT7059 / BXTS7059 Technical Reference Advanced Setup Chapter 2 Advanced Setup Introduction Select the Advanced menu item from the Aptio TSE screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as PCI Sub-System Settings, ACPI Settings, CPU Configuration, SATA or SAS Configuration, USB Configuration, and a Super IO configuration if the SHB is equipped with an optional IOB33.
Advanced Setup BXT7059 / BXTS7059 Technical Reference PCI Sub-System Settings (continued) Option Description PCI Common Settings PCI Latency Timer Timer value selections available: 32 PCI Bus Clocks, 64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI Bus Clocks, 192 PCI Bus Clocks, 224 PCI Bus Clocks, 248 PCI Bus Clocks VGA Pallet Snoop Disabled/Enabled PERR# Generation Disabled/Enabled SERR# Generation Disabled/Enabled PCI Express Settings There are several sections associated with this
BXT7059 / BXTS7059 Technical Reference Advanced Setup ACPI Settings Here are the ACPI soft control states available on the SHB. The standard BIOS default is the S1 only (CPU Stop Clock) sleep state. The SHB hardware and BIOS supports both the S1 and S3 sleep states and these sleep states are available for selection at the operating system level.
Advanced Setup BXT7059 / BXTS7059 Technical Reference CPU Configuration (continued) The core speed and 64-bit support status are two parameters for the specific Sandy Bridge-EN / Ivy BridgeEN processors installed on your SHB that are displayed on the second portion of this CPU configuration main menu. The lower portion of the main menu screen contains processor features that you may elect to enable or disable based on the unique requirements of your system.
BXT7059 / BXTS7059 Technical Reference Advanced Setup Runtime Error Logging Configuration Use this menu selection to enable or disable the runtime error logging support feature.
Advanced Setup BXT7059 / BXTS7059 Technical Reference Thermal Configuration This is sub-menu is an enable/disable selection for initializing the Intel® C604 thermal subsystem device.
BXT7059 / BXTS7059 Technical Reference Advanced Setup Floppy Disk Controller This option allows you to enable or disable the floppy drive controller on your platform. Option Description Disabled Set this value to prevent the BIOS from detecting the onboard floppy drive controller. Enabled Set this value to allow the BIOS to use the onboard floppy drive controller. This is the default setting.
Advanced Setup BXT7059 / BXTS7059 Technical Reference Super IO Configuration (continued) Parallel Port Configuration This option enables/disables the parallel port on the IOB33 and is used to configure the I/O address and operating mode for the parallel port. The default setting is AUTO, but you may elect to change this as needed. Option Description Parallel Port Enable/Disable - Set this value to disable prevent the parallel port from accessing any system resources.
BXT7059 / BXTS7059 Technical Reference Advanced Setup Serial Port Console Redirection Configuration The SHB must have an optional IOB33 installed in order for this BIOS setting to apply. Serial port console redirection is available for use on the IOB33’s COM0 and COM1 serial communication ports. Option Description Console Use this setting to specify how the system is to re-direct data to the out-of-band Redirection management port.
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BXT7059 / BXTS7059 Technical Reference Chipset Configuration Setup Chapter 3 Chipset Configuration Setup Introduction The term “chipset” is a bit of a misnomer for the Trenton BXT7059 and BXTS7059. The “chipset” on these SHBs is really a single component called a “Platform Controller Hub” or PCH, and the Trenton BXT7059 and BXTS7059 both feature the Intel® C604 PCH.
Chipset Configuration Setup BXT7059 / BXTS7059 Technical Reference PEX10 PCIe port Bifurcation Control: PICMG/PEX10 Port “Ax”: x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16 Port A0 Link Speed: GEN1, GEN2, GEN3 Port A1 Link Speed: GEN1, GEN2, GEN3 Port A2 Link Speed: GEN1, GEN2, GEN3 Port A3 Link Speed: GEN1, GEN2, GEN3 PEX10 PCIe port Data Direct I/O Control: PICMG/PEX10 Port A0: Disabled/Enabled PICMG/PEX10 Port A1: Disabled/Enabled PICMG/PEX10 Port A2: Disabled/Enabled PICMG/PEX10 Port A3: Disabled/Enabled Note:
BXT7059 / BXTS7059 Technical Reference Chipset Configuration Setup Memory configuration parameters continued: Patrol Scrub: Disabled/Enabled Demand Scrub: Disabled/Enabled Data Scrambling: Disabled/Enabled Device Tagging: Disabled/Enabled Rank Margin: Disabled/Enabled Thermal Throttling: Disabled, OLTT, CLTT OLTT Peak BW %: valid values are between 25 and 100, Default = 50 Altitude: Auto, 300M, 900M, 1500M, 3000M Serial Message Debug Level: Disabled, Minimum, Maximum, Trace, Memory Training DIMM Informati
Chipset Configuration Setup BXT7059 / BXTS7059 Technical Reference South Bridge Configuration (continued) PCI Express Ports These settings are available for configuring the PCI Express links used for Configuration component interconnects on the board and for the B0 PCIe link routed to the SHB’s edge connector. The default setting for each port is set to Auto and Trenton highly recommends leaving these settings alone.
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BXT7059 / BXTS7059Technical Reference Boot Setup Chapter 4 Boot Setup Introduction Select the Boot Setup menu item from the Aptio TSE screen to enter the BIOS Setup screen. The Boot menu option allows you to access the following the following boot setup features. Boot Configuration Enter the number of seconds you wish the board to wait for a setup key activation key.
Boot Setup BXT7059 / BXTS7059 Technical Reference CSM Parameters The Compatibility Support Module (CSM) parameters are used for BIOS compatibility with non-UEFI compliant operating systems.
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BXT7059 / BXTS7059Technical Reference Security Chapter 5 Security Two Levels of Password Protection Security Setup provides both a Supervisor and a User password. If you use both passwords, the Supervisor password must be set first. The system can be configured so that all users must enter a password every time the system boots or when Setup is executed, using either or either the Supervisor password or User password. The Supervisor and User passwords activate two different levels of password security.
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BXT7059 / BXTS7059 Technical Reference Saving & Exiting Setup Chapter 6 Saving and Exiting BIOS Setup and Restoring Defaults Introduction There are four methods of saving BIOS changes and leaving Aptio TSE listed at the top of this screen: 1 - Save Changes & Exit When you have completed the system configuration changes, select this option to save your BIOS changes and leave Aptio TSE. You will need to reboot the computer for the new system configuration parameters to take effect.
Saving & Exiting Setup BXT7059 &BXTS7059 Technical Reference The following menu options for BIOS defaults are available: Restore Defaults Aptio TSE automatically sets all Aptio TSE options to a complete set of factory default settings when you select this option. Select restore defaults from the Exit menu and press . Restore Defaults? [YES] [NO] appears in the window. Select YES to load restore defaults.
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BXT7059 / BXTS7059 Technical Reference Saving & Exiting Setup Chapter 7 Event Logs Change SMBIOS Event Log Settings Use the Aptio TSE menu screen options to set up the system event log reporting format and configuration options for the BIOS.
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BXT7059 / BXTS7059 Technical Reference Appendix A Appendix A BIOS Messages Introduction A status code is a data value used to indicate progress during the boot phase. These codes are outputted to I/O port 80h on the SHB. Aptio 4.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Status codes are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process.
Appendix A BXT7059 / BXTS7059 Technical Reference DXE Beep Codes # of Beeps 4 Description Some of the Architectural Protocols are not available 5 No Console Output Devices are found 5 No Console Input Devices are found 1 Invalid password 6 Flash update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met Trenton Systems Inc.
BXT7059 / BXTS7059 Technical Reference Appendix A BIOS Status Codes As the POST (Power On Self Test) routines are performed during boot-up, test codes are displayed on Port 80 POST code LEDs 0, 1, 2, 3, 4, 5, 6 and 7. These LED are located on the top of the SHB, just above the board’s battery socket. The POST Code LEDs and are numbered from right (position 1 = LED0) to left (position 8 – LED7). The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process.
Appendix A BXT7059 / BXTS7059 Technical Reference Status Code Ranges Status Code Range 0x01 – 0x0F 0x10 – 0x2F 0x30 – 0x4F 0x50 – 0x5F 0x60 – 0xCF 0xD0 – 0xDF 0xE0 – 0xE8 0xE9 – 0xEF 0xF0 – 0xF8 0xF9 – 0xFF Description SEC Status Codes & Errors PEI execution up to and including memory detection PEI execution after memory detection PEI errors DXE execution up to BDS DXE errors S3 Resume (PEI) S3 Resume errors (PEI) Recovery (PEI) Recovery errors (PEI) SEC Status Codes Status Code 0x0 Description Not use
BXT7059 / BXTS7059 Technical Reference Appendix A PEI Status Codes Status Code Description Progress Codes 0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13 Pre-memory CPU initialization (CPU module specific) 0x14 Pre-memory CPU initialization (CPU module specific) 0x15 Pre-memory North Bridge initialization is started 0x16 Pre-Memory North Bridge initialization (North Bridge module specific) 0x17 Pre-Memory
Appendix A BXT7059 / BXTS7059 Technical Reference PEI Error Codes 0x50 Memory initialization error. Invalid memory type or incompatible memory speed 0x51 Memory initialization error. SPD reading has failed 0x52 Memory initialization error. Invalid memory size or memory modules do not match. 0x53 Memory initialization error. No usable memory detected 0x54 Unspecified memory initialization error.
BXT7059 / BXTS7059 Technical Reference Appendix A PEI Beep Codes # of Beeps Description 1 Memory not Installed 1 Memory was installed twice (InstallPeiMemory routine in PEI Core called twice) 2 Recovery started 3 DXEIPL was not found 3 DXE Core Firmware Volume was not found 7 Reset PPI is not available 4 Recovery failed 4 S3 Resume failed DXE Status Codes Status Code A-7 Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime S
Appendix A BXT7059 / BXTS7059 Technical Reference 0x7A – 0x7F Reserved for future AMI DXE codes 0x80 – 0x8F OEM DXE initialization codes 0x90 Boot Device Selection (BDS) phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initiali
BXT7059 / BXTS7059 Technical Reference 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes Appendix A DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 South Bridge initialization error 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error.
Appendix A BXT7059 / BXTS7059 Technical Reference ACPI/ASL Status Codes Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is entering S5 sleep state 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xA
