User's Manual

Interfaces

Version 0.4

AMIMON Confidential 15

The following table specifies the timing parameters -

Table 7: Reset Timing Requirements

Symbol

Parameter Condition MIN TYP MAX Units

RST-CLK

Time from assertion of the HW reset until valid

clock is generated

40 MHz clock is valid – few

us after power up

300 ns

ST,RST

Time from assertion of the HW reset until the

STM32F completes the internal initialization

Power is stable 4.5 ms

INIT

Time from assertion of the HW/SW reset until the

AMN2110 completes the internal initialization

1.7 ms

The following figure specifies the reset schema and related signals -

Figure 11: Reset Mechanism