User's Manual

WHDI Connector Pins
Version 0.4
AMIMON Confidential 17
Chapter 4
WHDI Connector Pins
4.1 Signals
Table 8: WHDI Connector Signals
Direction
# of
Pins
Pin Name Description/Functionality Group
Tx
Remarks
30 D[29:0] 30-bit RGB (10:10:10) or YCrCb (10:10:10) Video In
1 DCLK Video data clock Video In Up to 78.125 MHz
1 DE Data enable Video In
1 H_SYNC Horizontal sync Video In
1 V_SYNC Vertical sync Video In
1 SPDIF SPDIF audio interface Audio In
1 SD I2S audio interface Serial Data signals Audio In
1 SCLK I2S continuous serial clock Audio In Up to 3.072Mbps
1 WS(LRCLK)
I2S Word Select (Left/right clock) which defines also the
sampling rate
Audio In
1 MCLK
I2S master clock coherent to WS according to specified
ratio
Audio NA
Rate is adjustable
on RX side
1 SDA Two-wire Serial Bus Data (Slave Mode) Control I/O Control I/F for WHDI
1 SCL Two-wire Serial Bus Clock (Slave Mode) Control In Control I/F for WHDI
1 INT Interrupt from WHDI module Control Out
1
RESET
Reset / Power-down line Control In
2 TBD[5:4]
TBD4, TBD5 are reserved in AMN11310, as an option for
RS232 connection to STM32F UART2.
TBD TBD
14 3.3V VCC Power Power
300 mA maximum
rating per pin
17 GND Ground Power Power
†
Data in this table is preliminary.