User's Manual

WHDI Connector Pins
Version 0.5
AMIMON Confidential 26
Chapter 4
WHDI Connector Pins
4.1 Signals
Table 9: WHDI Connector Signals
# of
Pins
Pin Name Description/Functionality Group Direction Remarks
30 D[29:0] 30-bit RGB (10:10:10) or YCrCb (10:10:10) Video Out
1 DCLK Video data clock Video Out Up to 78.125 MHz
1 DE Data enable Video Out
1 H_SYNC Horizontal sync Video Out
1 V_SYNC Vertical sync Video Out
1 SPDIF SPDIF audio interface Audio Out
1 SD I
2
S audio interface Serial Data signals Audio Out
1 SCLK I
2
S continuous serial clock Audio Out Up to 3.072Mbps
1 WS(LRCLK) I
2
S Word Select (Left/right clock) which defines
also the sampling rate
Audio Out
1 MCLK
I
2
S master clock coherent to WS according to
specified ratio
Audio Out
Rate is adjustable on RX
side
1 SDA Two-wire Serial Bus Data (Slave Mode) Control I/O Control I/F for WHDI
1 SCL Two-wire Serial Bus Clock (Slave Mode) Control In Control I/F for WHDI
1 INT Interrupt from WHDI module Control Out
1
RESET
Reset / Power-down line Control In
1 MUTE (TBD6) MUTE signal Audio Out
Signals audio error and can
be used by the next audio
device down the line to
mute the audio when errors
occur
2 TBD[5:4]
TBD4, TBD5, are reserved in, AMN12310 as an
option for RS232 connection to STM32F UART2.
TBD TBD
8 3.3V VCC Power Power 300 mA maximum rating per
pin
17 GND Ground Power Power