User`s guide

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User's Guide Babyface © RME
26.6 Noise Level in DS / QS Mode
The outstanding signal to noise ratio of the Babyface's AD-converters can be verified even with-
out expensive test equipment, by using record level meters of various software. But when acti-
vating the DS and QS mode, the displayed noise level will rise from -109 dB to -104 dB at 96
kHz, and –82 dB at 192 kHz. This is not a failure. The software measures the noise of the whole
frequency range, at 96 kHz from 0 Hz to 48 kHz (RMS unweighted), at 192 kHz from 0 Hz to 96
kHz.
When limiting the measurement range from 20 Hz to 20 kHz (so called audio bandpass) the
value would be -110 dB again. This can be verified with RME's DIGICheck. The function Bit
Statistic & Noise measures the noise floor by Limited Bandwidth, ignoring DC and ultrasound.
The reason for this behaviour is the noise shaping technology of the analog to digital convert-
ers. They move all noise and distortion to the inaudible higher frequency range, above 24 kHz.
That’s how they achieve their outstanding performance and sonic clarity. Therefore the noise is
slightly increased in the ultrasound area. High-frequency noise has high energy. Add the dou-
bled (quadrupled) bandwidth, and a wideband measurement will show a significant drop in
SNR, while the human ear will notice absolutely no change in the audible noise floor.
26.7 SteadyClock
The SteadyClock technology of the Babyface guarantees an excellent performance in all clock
modes. Thanks to a highly efficient jitter suppression, the AD- and DA-conversion always oper-
ates on highest sonic level, being completely independent from the quality of the incoming clock
signal.
SteadyClock has been originally developed
to gain a stable and clean clock from the
heavily jittery MADI data signal (the embed-
ded MADI clock suffers from about 80 ns
jitter). Using the Babyface's input signals
SPDIF and ADAT, you'll most probably
never experience such high jitter values. But
SteadyClock is not only ready for them, it
would handle them just on the fly.
Common interface jitter values in real world
applications are below 10 ns, a very good
value is less than 2 ns.
The screenshot shows an extremely jittery
SPDIF signal of about 50 ns jitter (top
graph, yellow). SteadyClock turns this signal into a clock with less than 2 ns jitter (lower graph,
blue). The signal processed by SteadyClock is of course not only used internally, but also used
to clock the digital output. Therefore the refreshed and jitter-cleaned signal can be used as ref-
erence clock without hesitation.