Specifications

CoreModule/PC Technical Manual
4-6
In many cases, the module's ROM-BIOS functions provide all of the services that you will need to
control and access devices on the module and connected to its I/O interfaces. If direct programming
of the module's peripheral interfaces is necessary, refer to one of the many available references on
programming the IBM PC and XT for details on programming the standard functions.
4.3.1 CPU
The module’s central processor unit (CPU) is an 8088-compatible device, but is implemented in low
power CMOS logic.
The CoreModule/PC is designed to operate at an effective clock rate of 9.8 MHz.
4.3.2 ROM-BIOS Device
A single EPROM device contains the module's PC compatible ROM-BIOS. The device is normally
a 27C512 EPROM. All accesses are made 8 bits at a time. This device has an access time of
250 nS or less.
The ROM-BIOS occupies the memory area from F0000h through FFFFFh.
4.3.3 Onboard DRAM
The module is shipped with either 1 megabyte or 256 kilobytes of system DRAM. The
CoreModule/PC does not employ a memory parity bit.
DRAM refresh is accomplished in the standard manner. A 15 uS time-base generator and a counter
for refresh addresses within the module's control logic provide refresh.
4.3.4 Interrupt Controller
The CoreModule/PC features an interrupt controller equivalent to the 8259A. This PC- compatible
controller provides eight prioritized interrupt levels. Several are normally associated with the
module's onboard device interfaces and controllers, and several are available on the PC expansion
bus. Table 4-3 lists the typical interrupt level usage. Note that IRQ0 and IRQ1 are for internal use
only and are not available on the expansion bus.