Specifications

Advanced Topics
4-7
Interrupt Location Typical Use
IRQ0 CoreModule/PC Counter/Timer
IRQ1 CoreModule/PC Keyboard
IRQ2 Bus EGA/VGA Option*
IRQ3 Bus Secondary Serial Port (COM2)
IRQ4 CoreModule/PC Primary Serial Port (COM1)
IRQ5 Bus Secondary Parallel Port (LPT2)**
IRQ6 Bus Floppy Controller
IRQ7 CoreModule/PC Primary Parallel Port (LPT1)**
* This interrupt is sometimes assigned to a VGA controller, but is normally
not required on Ampro VGA adapters.
** The printer port interrupt is normally disabled and available for other
Table 4-3. Interrupt Level Assignments
4.3.5 DMA Controller
An “8237-like” DMA controller function is implemented within the module's control logic,
resulting in three available DMA channels. DMA transfers can be in blocks as large as 64K bytes.
As in a standard PC, addresses A0-A15 are generated directly by the DMA controller logic, while
addresses A16-A19 are generated by PC-compatible DMA page registers. The DMA channels are
used on the CoreModule/PC as indicated in Table 4-4.
DMA Limitations
From a software perspective, the module's three-channel DMA controller is PC-compatible. It may
be programmed in the same manner as a standard 8237, and should run existing driver and
application software without modification. However, from a hardware perspective, the following
limitations apply:
+ Devices on the PC/104 bus that require DMA operation must implement the Terminal Count
(TC) signal. Specifically, this means they must stop issuing DRQ's once the CPU asserts the TC
signal on the PC/104 bus. As an example, the Ampro MiniModule/FSS (which requires DMA
for its operation) can be jumpered to support TC, and can therefore be used to provide SCSI
hard disk expansion.
+ DMA operations may not use "upper memory" addresses (i.e. addresses above 640K) on the
PC/104 bus as their destination. For example, data may not be transferred from a SCSI hard
disk (connected to a MiniModule/FSS) directly to video RAM, via DMA. An alternative would
be to transfer the data from the disk to system RAM via DMA, and then from system RAM to
video RAM via a block move (using programmed I/O).