Specifications

B-1
APPENDIX B
BUS TIMING
INTRODUCTION
The following table and figures are provided to show the timing relationships of signals on the
CoreModule/PC's PC bus interface during memory and I/O transfers.
Ref Type Description Min ns Max ns
1 M/IO BALE pulse width 61
2 M/IO SA setup to -IOx or -SMEMx 102
3 M/IO Command Width 541
4 M/IO Read data access 482
5 M/IO Write data setup 7
6a M Command deasserted 170
6b M/IO Command deasserted 170
7a IO Read data hold 0
7b M/IO Write data hold 25
8 M/IO Read command to SD disabled 30
9 M/IO IOCHRDY valid from command
asserted
373
10 M/IO IOCHRDY deasserted pulse width 125 15600
11 M/IO Command hold from IOCHRDY 125
12 M/IO BALE asserted from command
deasserted
46
13 M/IO Clock period (Tclk) 275 285
14 M/IO Data setup to
IOCHRDY deasserted
75
15 M/IO SA Hold 53
Table B-1. Memory and I/O Timing