Computer Hardware User Manual

2–40
Table 2– 30 lists the signals available on connector J3. Table 2– 31 shows compatible mating
connectors to J3.
Table 2– 30. Flat Panel Video Connector (J3)
Pin
Signal
Name Description
2, 34, 37 +3.3V Panel power
3 +12V +12 Volt supply (from J10)
5 ShfClk Shift Clock. Pixel clock for flat panel data.
7 M DE M signal for panel AC drive control. Sometimes called ACDCLK or AC Drive.
May also be configured to be -BLANK or as Display Enable (DE) for TFT
panels.
9 LP Latch Pulse. Sometimes called Load Clock, Line Load, or Input Data Latch.
It’s the flat panel equivalent of HSYNC.
10 FLM First Line Marker. Also called Frame Sync or Scan Start-up. Flat panel
equivalent to VSYNC.
12–31 FP0-
FP19
Flat panel video data 0 through 19 (in order).
32, 33 +5V +5 Volt supply from Little Board/P5x
35 ENABLK Enable backlight. Power control for panel backlight. Active high.
36 EBKL* Enable backlight. Power control for panel backlight. Active low.
38 ENAVEE Enable Vee, active high. Power sequencing control for panel bias voltage.
This signal is sent to the optional Vee supply board to control Vee output.
39 ENAVDD Enable Vdd. Power sequencing control for panel driver electronics Vdd.
Active high. This signal is used to switch VDVP (pin 44).
41 FP20 Video data 20
42 FP21 Video data 21
43 FP22 Video data 22
44 VDDP Switched V_LCD supply to panel
45 FP23 Video data 23
46 VEE Switched Vee supply to panel (from LCD Bias Supply option board or your
own switched supply).
47 ECONT External contrast adjustment voltage. This is an input to the flat panel to
control the panel contrast ratio. The Ampro LCD Bias Supply option board
provides this signal and a means of attaching an external contrast
adjustment pot.
50 +12SAFE Switched +12V supply to backlight power converter.
1, 4, 6, 8,
11, 40, 48,
49
Ground Ground