Specifications

SCPI GPIB COMMAND STATUS MODEL
The above figure shows the status register structure of the power supply. The Standard Event, Status Byte, and
Service Request Enable registers perform standard GPIB functions. The Operation Status, Questionable Status,
and Protection Event Status registers implement status functions specific to the power supplies. Bit configuration
for each register is also shown in the above figure.
Operation status register
The Operation Status Condition register latches any operation condition that is passed to the power supply by
users. It is a read-only register. Use “STAT:OPER?” query to read the register, but not clear it.
Questionable Status group
The Questionable Status group consists of two registers. The Questionable Status Event register holds real-time
status of the power supply. It is a read-only register. Use “STAT:QUES?” query to read it, but not clear it. The
Questionable Status Enable register is a mask for enabling specific bits from the Questionable Event register to
set the Questionable Data (QD) bit of the Status Byte register. This bit (bit 3) is the logical OR of all the
Questionable Event register bits that are enabled by the Questionable Status Enable register. Use
“STAT:QUES:ENAB” command to set or read this register.
Standard Event Status group
Standard Event Status group consists of an Event register and an Enable register that are programmed by
COMMON commands. The Standard Event register latches events relating to interface communication status. It
is a read-only register. The Standard Event Enable register functions similarly to the enable registers of the
Questionable Status Enable register. The common “*ESE” command programs specific bits in the Standard
Event Status Enable register. “*ESR?” reads the Standard Event Status Event register. Reading the register
clears it.
Status byte and Service Request Enable registers
Status Byte register summarizes the information from all other status groups. The register can be read by
“*STB?”. Whenever the power supply requests service, it sets the SRQ interrupt line true and latches RQS into
bit 6 of the Status Byte register. When the controller services the interrupt, RQS is cleared inside the register and
returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed. No bits
of the Status Byte register are cleared by reading it.
Service Request Enable register determines which bits from the Status Byte register are allowed to generate SRQ
using “*SRE” common command.
Users can determine the reason for an SRQ by the following actions:
x Use the “*STB?” query to determine which summary bits are active.
x Read the corresponding Event register for each summary bit to determine which events caused the
summary bit to be set. If it is caused by Questionable Data (QD) bit of the Status Byte register, users
must read the Protection Event Status register to determine the actual channel number where the
SRQ is generated.
x The interrupt will recur until the specific condition that caused the event is removed.
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