Unit installation

MAX+PLUS II Getting Started
298 Altera Corporation
MAX+PLUS II Text Editor or any standard
text editor, then compile, simulate, and
program your projects within
MAX+PLUS II. AHDL supports Boolean
equation, state machine, conditional, and
decode logic. AHDL also allows you to
create and use parameterized functions,
and includes full support for functions in
the Library of Parameterized Modules
(LPM).
Text Design Export files (.tdx) and Text
Design Output Files (.tdo) generated by the
MAX+PLUS II Compiler are also written in
AHDL syntax.
Altera Megafunction Partner Program
(AMPP) A program that offers support to
third-party vendors to create and
distribute megafunctions for use with
MAX+PLUS II. You must enter a password
in the Megacore/AMPP Licenses dialog
box (accessed through the Authorization
Code command on the Options menu) to
enable a particular megafunction for
implementation in a design file.
Additionally, some vendors may provide
the option to view and edit a megafunction
design file.
For information on current AMPP vendors,
available megafunctions, and passwords,
contact Altera Marketing.
ancillary file A file that is associated with
a MAX+PLUS II project, but is not a design
file in the project hierarchy tree. Most
ancillary files also do not contain design
logic. User-editable ancillary files with the
same filename as the project appear in the
Hierarchy Display window. See the
following list:
Editable Ancillary Files:
Assignment & Configuration File (.acf)
Assignment & Configuration Output File
(.aco)
Command File (.cmd)
EDIF Command File (.edc)
Fit File (.fit)
FLEX Chain File (.fcf)
Hexadecimal (Intel-format) File (.hex)
History File (.hst)
Include File (.inc)
Jam File (.jam)
JTAG Chain File (.jcf)
Library Mapping File (.lmf)
Log File (.log)
Memory Initialization File (.mif)
Memory Initialization Output File (.mio)
Message Text File (.mtf)
Programmer Log File (.plf)
Report File (.rpt)
Serial Vector Format File (.svf)
Simulator Channel File (.scf)
Standard Delay Format (SDF) Output File
(.sdo)
Symbol File (.sym)
Table File (.tbl)
Tabular Text File (.ttf)
Text Design Export File (.tdx)
Text Design Output File (.tdo)
Timing Analyzer Output File (.tao)
Vector File (.vec)
VHDL Memory Model Output File (.vmo)
Non-Editable Ancillary Files:
Compiler Netlist File (.cnf)
Hierarchy Interconnect File (.hif)
JEDEC File (.jed)
Node Database File (.ndb)
Programmer Object File (.pof)
Raw Binary File (.rbf)
Serial Bitstream File (.sbf)
Simulator Initialization File (.sif)
Simulator Netlist File (.snf)
SRAM Object File (.sof)
81_GSBOOK.fm5 Page 298 Tuesday, October 14, 1997 4:04 PM