Unit installation

Glossary
Altera Corporation 303
Glossary
Glossary
Command File (.cmd) An ASCII text file
(with the extension .cmd) that contains
commands for batch-mode simulation.
comment In the Graphic and Symbol
Editors, a comment is a free-floating block
of text used to document the design. It is
not associated with any object. A comment
stands alone anywhere within Graphic
Editor files. A comment also stands alone
within the symbol border of a Symbol
Editor file. Comments are ignored by the
Compiler, and can be used to document
various sections of a file.
In the Waveform Editor, a comment is a
line of text used to annotate the waveforms
in the waveform drawing area . It is not
associated with any waveform. A comment
is anchored to the time on the time scale
where the first character is entered. A label
appears in the Name field to indicate a
comment line; when a comment is added
between two existing nodes, it appears in a
blank space, which is inserted between the
waveforms. Comments are ignored by the
Compiler.
In all MAX+PLUS II text files except VHDL
Design Files (.vhd), Verilog Design
Files (.v), and Assignment &
Configuration Files (.acf), e.g., in Report
Files (.rpt), Vector Files (.vec), and Text
Design Files (.tdf), a comment is any string
of characters enclosed in percent symbols
(%). You can insert comments wherever
white space is allowed in text files.
In VHDL Design Files and ACFs,
comments begin with two dashes (--) and
continue to the End-of-Line. AHDL TDFs
also support VHDL-style comments. If you
use a VHDL-style comment in a TDF, you
must separate the two dashes from any
preceding symbolic name with at least one
space.
In Verilog Design Files, comments begin
with two slashes (//) and continue to the
End-of-Line. Verilog Design Files and
ACFs also support comments consisting of
any string of characters enclosed between
/* and */ characters.
Compiler Netlist File (.cnf) A binary file
(with the extension .cnf) that contains the
data from a design file. The CNF is created
by the Compiler Netlist Extractor module
of the MAX+PLUS II Compiler.
Configuration EPROM AlteraÕs family of
serial EPROMs, which are designed to
configure FLEX 6000, FLEX 8000, and
FLEX 10K devices. This device family
includes the EPC1, EPC1213, EPC1064,
EPC1064V, and EPC1441 devices.
connection dot A dot entered at an
intersection of two signal lines (nodes or
buses) in a Graphic Editor file. The
connection dot indicates that the signals
are logically connected.
construct A unit in a text design language
such as AHDL, VHDL, Verilog HDL, or
EDIF.
continuity checking A test for open circuits
between device pins and programming
adapter sockets. This test verifies that a
device is properly seated in the socket of
the adapter.
cutoff node A node that is excluded from
timing analysis. The signal associated with
a node can be cut off from a timing analysis
by tagging it with the Timing Analysis
Cutoff command.
81_GSBOOK.fm5 Page 303 Tuesday, October 14, 1997 4:04 PM