Unit installation

MAX+PLUS II Getting Started
304 Altera Corporation
D
database A flattened representation of all
design files in a MAX+PLUS II project
hierarchy. The database is used internally
by Compiler modules during compilation.
decimal The base 10 number system
(radix). Decimal digits are 0 through 9.
In AHDL,VHDL, and Verilog HDL no
special notation is needed to indicate
decimal digits.
default Simulator Channel File (.scf) A
Simulator Channel File (.scf) that can
contain all nodes and groups that are in the
Simulator Netlist File (.snf) for a project. It
is created automatically with the Enter
Nodes from SNF command (Node menu)
in the Waveform Editor.
default timing tagging The Timing
Analyzer provides the following default
node tagging for timing analysis:
delimiter A text string, character, or
keyword used to define the beginning or
the end of a statement or construct in a text
file.
For example, [ and ] are delimiters of
AHDL group ranges and % is a comment
delimiter in many MAX+PLUS II text files.
design file A file that contains logic for a
MAX+PLUS II project and is compiled by
the Compiler. The following files are
design files:
■ Altera Design File (.adf)
■ EDIF Input File (.edf) *
■ Graphic Design File (.gdf) *
■ OrCAD Schematic File (.sch) *
■ State Machine File (.smf)
■ Text Design File (.tdf) *
■ Verilog Design File (.v)
■ VHDL Design File (.vhd) *
■ Waveform Design File (.wdf)
■ Xilinx Netlist Format File (.xnf)
An asterisk (*) indicates the design files
that can exist as top-level files in
hierarchical projects. Other design files
must be the only design file in a project or
must exist at the bottom level of a
hierarchical project.
destination node A node that is tagged
(designated) as the destination of a signal
for the purpose of timing analysis. A
destination node is tagged with the Timing
Analysis Destination command (Utilities
menu), and can be any node that is the
input to a logic function or a pin.
device A device refers to an Altera
programmable logic device, including
Classic, MAX 5000, MAX 7000, MAX 9000,
Analysis Mode: Default Tagging:
Delay Matrix All input pins are
sources; all output pins
are destinations.
Setup/Hold
Matrix
All input pins are
sources; all data and
Clock inputs to
registers, Latch Enable
inputs to latches, and
data, address, and Write
Enable inputs to
asynchronous RAM are
destinations.
Registered
Performance
All Q outputs of
registers are sources; all
data and Clock Enable
inputs to registers are
destinations.
81_GSBOOK.fm5 Page 304 Tuesday, October 14, 1997 4:04 PM