Unit installation

MAX+PLUS II Getting Started
306 Altera Corporation
Dynamic models allow a simulation to run
faster; however, the Compiler requires
additional time to generate the SNF.
E
EAB see Embedded Array Block.
EC see embedded cell.
EDIF Electronic Design Interchange
Format. An industry-standard format for
the transmission of design data.
You can generate an EDIF 2 0 0 or 3 0 0
netlist file from a schematic design or from
a VHDL or Verilog HDL design that has
been processed with an appropriate
industry-standard synthesis tool and then
import the file into MAX+PLUS II as an
EDIF Input File (.edf). MAX+PLUS II
supports EDIF Input Files that contain
functions from the Library of
Parameterized Modules (LPM). The
MAX+PLUS II Compiler can also generate
one or more EDIF Output Files (.edo) in
either EDIF 2 0 0 or 3 0 0 format that contain
functional or timing information for
simulation with a standard EDIF
simulator.
The MAX+PLUS II CompilerÕs EDIF
Netlist Reader and EDIF Netlist Writer
modules have been awarded the Electronic
Industries AssociationÕs (EIA) EDIF
version 3 0 0 Self-Verification Seal of
Approval. This award indicates that
MAX+PLUS II EDIF 3 0 0 support has
successfully completed the testing process
to ensure compliance with the EDIF 3 0 0
Netlist View standard.
EDIF Command File (.edc) An ASCII text
file (with the extension .edc) used to
customize the format of EDIF Output Files
(.edo) created by the CompilerÕs EDIF
Netlist Writer module.
EDIF Input File (.edf) An EDIF version 2 0 0
or 3 0 0 netlist file generated by any
standard EDIF netlist writer. EDIF Input
Files (with the extension .edf) can be
compiled by the MAX+PLUS II Compiler.
MAX+PLUS II supports EDIF Input Files
that contain functions from the Library of
Parameterized Modules (LPM).
EDIF Output File (.edo) An EDIF version
2 0 0 or 3 0 0 netlist file (with the extension
.edo) generated by the EDIF Netlist Writer
module of the Compiler. This file can be
exported to an industry-standard UNIX
workstation or PC environment for
simulation.
EEPROM Electrically Erasable
Programmable Read-Only Memory. A
form of reprogrammable semiconductor
memory in which the contents (program)
can be erased by subjecting the device to
appropriate electrical signals.
Embedded Array Block (EAB) A physically
grouped set of 8 embedded cells that
implement memory (RAM or ROM) or
combinatorial logic in a FLEX 10K device.
An EAB consists of an embedded cell array,
with data, address, and control signal
inputs and data outputs that are optionally
registered.
A single EAB can implement a memory
block of 256 × 8, 512 × 4, 1,024 × 2, or
2,048 × 1 bits. Each embedded cell within
the EAB implements up to 256 bits of
memory. For memory blocks of these sizes,
an EAB has 8, 4, 2, or 1 outputs,
respectively. Multiple EABs can be
combined to create larger memory blocks.
81_GSBOOK.fm5 Page 306 Tuesday, October 14, 1997 4:04 PM