Unit installation

Glossary
Altera Corporation 309
Glossary
Glossary
You can also display a read-only version of
Fit File information from the most recent
project compilation in the Floorplan Editor.
FLEX Chain File (.fcf) An ASCII file (with
the extension .fcf) that stores programming
file names for use in configuring multiple
FLEX 6000, FLEX 8000, or FLEX 10K
devices in a Passive Serial configuration
scheme. An FCF saves the information
entered with the ProgrammerÕs Multi-
Device FLEX Chain Setup command
(FLEX menu).
FLEX 6000 An Altera device family based
on Flexible Logic Element MatriX
architecture. This SRAM-based family
offers high-performance, register-
intensive, high-gate-count devices. The
FLEX 6000 device family includes the
EPF6016 device.
FLEX 8000 An Altera device family based
on Flexible Logic Element MatriX
architecture. This SRAM-based family
offers high-performance, register-
intensive, high-gate-count devices. The
FLEX 8000 device family includes the
EPF8282V, EPF8282A, EPF8282AV,
EPF8452A, EPF8636A, EPF8820A,
EPF81188A, and EPF81500A devices.
1 Altera recommends using
FLEX 8000A devices rather than
FLEX 8000 devices for all new
designs.
FLEX 10K An Altera device family based
on Flexible Logic Element MatriX
architecture. This SRAM-based family
offers high-performance, register-
intensive, high-gate-count devices with
embedded arrays. The FLEX 10K device
family includes the EPF10K100, EPF10K70,
EPF10K50, EPF10K40, EPF10K30,
EPF10K20, and EPF10K10 devices.
FLEX 10K devices, which include
EPF10K50V, EPF10K130V, and
EPF10K250A devices, are enhanced
versions of FLEX 10K devices, and are
function-, pin-, and programming-file-
compatible with FLEX 10K devices.
FLEX 10KA devices differ from FLEX 10K
devices in that they are 3.3-V versions of
FLEX 10K devices.
The EPF10K100GC503-3DX device
includes built-in ClockLock and
ClockBoost phase-locked loop circuitry.
flipflop or register An edge-triggered,
clocked storage unit that stores a single bit
of data. A low-to-high transition on the
Clock signal changes the output of the
flipflop, based on the value of the data
input(s). This value is maintained until the
next low-to-high transition of the Clock, or
until the flipflop is preset or cleared.
Depending on the architecture of the
device family, a register can be
programmed as a level-sensitive flow-
through latch or as an edge-triggered D,T,
JK, or SR flipflop.
In Verilog HDL, ÒregisterÓ is also used to
describe the abstraction of a data storage
device that the MAX+PLUS II Compiler
uses to infer registers.
f
MAX
(maximum Clock frequency) The
maximum Clock frequency that can be
achieved without violating internal setup
and hold time requirements.
f
MAX
is also a timing assignment that
specifies the minimum acceptable Clock
frequency. In MAX+PLUS II, you can
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