Unit installation

MAX+PLUS II Getting Started
310 Altera Corporation
specify a required f
MAX
for an entire
project and/or for any input pin (INPUT or
INPUTC), bidirectional pin (BIDIR or
BIDIRC input function), or a register.
Function Prototype Specifies the ports
(pinstubs) of a primitive, megafunction, or
macrofunction in AHDL. A Function
Prototype consists of the name of the
function, and a list of its inputs and
outputs. For mega- and macrofunctions,
the Function Prototype can also contain
parameters that are used to specify the
characteristics of the function. Function
Prototypes are specified in the Function
Prototype Statement. They are often stored
in Include Files (.inc). Include Files that
contain Function Prototypes for Altera-
provided mega- and macrofunctions are
located in the \maxplus2\max2lib\
mega_lpm and \maxplus2\max2inc
directories created during installation,
respectively. (On a UNIX workstation, the
maxplus2 directory is a subdirectory of the
/usr directory.)
To implement an instance of a mega- or
macrofunction in AHDL, its logic must be
defined in a design file and its Function
Prototype must be declared. (Function
Prototypes are optional for primitives.)
You can then create an instance of the
function with an Instance Declaration or an
in-line reference.
1 When you use a Module
Instantiation in Verilog HDL, the
MAX+PLUS II Compiler uses the
port name and ordering information
in AHDL Include Files that contain
Function Prototypes to implement
an instance of the logic function.
G
GDF see Graphic Design File.
glitch or spike A signal value pulse that
occurs when a logic level changes two or
more times over a short period.
When the Simulator is in timing or linked
simulation mode, you can define the length
of a glitch and monitor the project for
pulses shorter than the defined value.
Glitch detection is not available in
functional simulation mode.
global signal A pin- or logic-driven signal
that passes through the global routing on a
device before performing its specified
function. Clock, Preset, Clear, and Output
Enable signals can be global signals.
1 Logic-driven global signals are
available only in FLEX 6000 devices.
A global signal can be set in various ways:
■ During design entry with a GLOBAL
primitive. You can use a dedicated
input pin to drive a global signal
directly by feeding its output directly
to a GLOBAL primitive. You can also
use the output of a logic function as a
global signal by feeding its output
directly to a GLOBAL primitive. A logic-
driven global signal consumes a
dedicated global input pin.
■ With the Automatic Global option in the
Global Project Logic Synthesis dialog
box (Assign menu). The Compiler
chooses the pin-driven signal that
feeds the most flipflops as a global
Clock, Preset, or Clear, and the signal
that feeds the most TRI buffers is
chosen as the global Output Enable.
81_GSBOOK.fm5 Page 310 Tuesday, October 14, 1997 4:04 PM