Unit installation

Glossary
Altera Corporation 311
Glossary
Glossary
■ With the Global Signal logic option in
the Individual Logic Options dialog
box, which you can open from the
Logic Options dialog box (Assign
menu). When this option is turned on
for an input pin or for a single-output
logic function, it is equivalent to using
a GLOBAL primitive. Turning this logic
option off prevents an input pin from
being used as a global signal.
GND A low-level input voltage.
GND is the default inactive node value. In
an AHDL Text Design File (.tdf), GND is
used as a predefined constant and
keyword. In a VHDL Design File (.vhd),
GND is represented by '0'. In a Verilog
Design File (.v), GND is represented by 0 . In
a Graphic Editor file, GND is a primitive
symbol. GND is represented as a low (0)
logic level in the Simulator and Waveform
Editor.
Graphic Design File (.gdf) A schematic
design file (with the extension .gdf) created
with the MAX+PLUS II Graphic Editor.
An OrCAD Schematic File (.sch) is
automatically translated into a GDF and
treated as a GDF in the MAX+PLUS II
Graphic Editor and Compiler.
Gray code A counting scheme in which
only one bit at a time changes value
between consecutive count values. In
contrast, a binary count sequence does not
preclude more than one bit changing at
consecutive count values. When only one
bit changes, noise susceptibility is reduced
in the circuit.
group or array In AHDL, a group is a
collection of up to 256 symbolic names that
are treated as a unit. A group name can be
specified with a single-range group name,
dual-range group name, or sequential
group name format.
In VHDL, a group is called an array, and is
not limited to 256 symbolic names.
Examples of array types are
STD_LOGIC_VECTOR and BIT_VECTOR.
See Section 3.2.1: Array Types in the IEEE
Standard VHDL Language Reference
Manual for more information. Only one-
and two- dimensional arrays of scalar
elements are supported.
In Verilog HDL, a group is called an array,
and is limited to 256 symbolic names.
Examples of array types are memories
(which are arrays of register elements or
words) and arrays of gate instances and
registers. The elements, instances, or
registers in the array are specified with a
range. See Section 3.3: Vectors, Section 3.8:
Memories, and Section 7: Gate and Switch
Level Modeling in the IEEE Standard
Hardware Description Language Based on
the Verilog Hardware Description
Language manual for more information.
In the Waveform Editor and Simulator, a
group is a collection of up to 256 nodes that
are treated as a unit. In these applications,
a group name can be specified with an
arbitrary group name or single-range
group name format.
group name see bus name.
H
hard logic function A logic function in a
design file that is not removed during
standard logic synthesis and therefore can
be assigned to a physical resource such as a
specific device, pin, logic cell, or I/O cell.
81_GSBOOK.fm5 Page 311 Tuesday, October 14, 1997 4:04 PM