Unit installation

MAX+PLUS II Getting Started
312 Altera Corporation
In Graphic Design Files (.gdf) and Text
Design Files (.tdf), hard logic primitives/
ports include INPUT, INPUTC, OUTPUT,
OUTPUTC, BIDIR, BIDIRC, LCELL,
MCELL, DFF, DFFE, TFF, TFFE,JKFF,
JKFFE, SRFF, SRFFE, and LATCH.
However, INPUT and INPUTC primitives
that do not affect project outputs are not
considered to be hard logic functions.
When SOFT, TRI, and OPNDRN primitives
are not removed during logic synthesis,
they are also hard logic primitives. A
megafunction or macrofunction that
contains a hard logic primitive is
considered to be a hard logic function.
In Waveform Design Files (.wdf), hard
logic functions are input nodes and output
and buried nodes with registered and
combinatorial node types.
hexadecimal The base 16 number system
(radix). Hexadecimal digits are 0 through 9
and A through F.
Hexadecimal numbers are indicated with
the following notation:
Examples:
H
"123AECF" (AHDL)
16#FF# (VHDL)
'h837FF (Verilog HDL)
Hexadecimal (Intel-Format) File (.hex) An
ASCII text file (with the extension .hex) in
the Intel hexadecimal format.
The MAX+PLUS II Compiler and
Simulator can use Hex Files as inputs to
specify the initial contents of a memory
(e.g., a ROM).
The MAX+PLUS II Compiler automatically
creates output Hex Files containing
configuration data for the Active Parallel
Up (APU) configuration scheme for
FLEX 8000 devices, and the Passive Serial
(PS) configuration scheme for FLEX 6000
and FLEX 10K devices.
After compilation, you can also create Hex
Files that support other configuration
schemes for FLEX 6000, FLEX 8000, and
FLEX 10K devices.
1 If your project uses memory and you
use a Hex File to specify its initial
contents, you should name the file
with a name that is not the same as
the project name or any chip name
within the project. Because the
Compiler automatically generates
Hex Files as outputs for FLEX 6000,
FLEX 8000, and FLEX 10K devices,
these output files may overwrite
your initial memory content files.
hierarchical node or symbol name The
unique name for a node or symbol that is
based on its location in the hierarchy of
design files and the net ID number or the
AHDL,VHDL, or Verilog HDL instance
name of the logic function to which it is
connected.
Every node and symbol in a project has a
hierarchical name; you can also assign a
node name or a probe name to a node.
Language Notation
AHDL X"<series of digits 0 to 9 , A to F >"
or
H"<series of digits 0 to 9 , A to F >"
VHDL 16#<series of digits 0 to 9 , A to F >#
Verilog HDL 'h<series of digits 0 to 9 , A to F >
81_GSBOOK.fm5 Page 312 Tuesday, October 14, 1997 4:04 PM