Unit installation

MAX+PLUS II Getting Started
314 Altera Corporation
Programmer. The Programmer also
provides the capability to configure one or
more FLEX 10K devices in a JTAG chain
and one or more FLEX 6000, FLEX 8000, or
FLEX 10K devices in a FLEX chain.
in-system programmability (ISP) The
capability of EEPROM-based devices, such
as AlteraÕs MAX 9000 and MAX 7000S
devices, to be programmed after they have
been mounted on a printed circuit board.
The MAX+PLUS II Programmer supports
in-system programming via the BitBlaster
serial download cable and the ByteBlaster
parallel download cable. The Programmer
also provides the capability to program
multiple devices in a JTAG chain.
Include File (.inc) An ASCII text file (with
the extension .inc) that can be imported
into a Text Design File (.tdf) by an AHDL
Include Statement. The Include File
replaces the Include Statement that calls it.
Include Files can contain Function
Prototype, Define, Parameters, or Constant
Statements. Include Files that contain
Function Prototypes for Altera-provided
mega- and macrofunctions are located in
the \maxplus2\max2lib\mega_lpm and
\maxplus2\max2inc directories created
during installation, respectively. (On a
UNIX workstation, the maxplus2 directory
is a subdirectory of the /usr directory.)
1 When you use a Module
Instantiation in Verilog HDL, the
MAX+PLUS II Compiler uses the
port name and ordering information
in AHDL Include Files that contain
Function Prototypes to implement
an instance of the logic function.
insertion point The location at which text
or graphics are inserted.
In a dialog box or in the Text Editor
window, the insertion point appears as a
flashing vertical bar. In the Graphic or
Symbol Editor, it appears as a flashing
square. In the Waveform Editor, an
insertion point in the waveform drawing
area appears as a short horizontal line that
extends to the right of the Time cursor. In
the node/group information area, a name
or blank space that is selected is interpreted
as an insertion point.
When you type text, it appears to the left of
the insertion point, which moves to the
right as you type. When you enter or paste
symbols or waveforms, the upper left
corner of the item(s) appears at the
insertion point.
instance The use of a logic function in a
design file. In the Graphic Editor, the
instance is represented by the symbol (net)
ID number in the lower left corner; in the
Waveform Editor, it is the name of the
node. In AHDL, instances are declared in
one of two forms: an Instance Declaration
that declares a variable of the type
<primitive>, <megafunction>, or
<macrofunction>, or an in-line logic
function reference. In VHDL, instances of
logic functions are declared with a
Component Instantiation Statement;
registers can also be implemented with
Register Inferences. In Verilog HDL,
instances are declared with Module
Instantiations and Gate Instantiations.
In the Hierarchy Display, an instance of a
mega- or macrofunction is represented by
the function name, followed by a colon (:)
and a net ID number. In an AHDL Variable
Declaration and a VHDL Component
Instantiation Statement, an instance is
represented by the instance name followed
by a colon and the function name. In a
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