Unit installation

Glossary
Altera Corporation 315
Glossary
Glossary
Verilog HDL Module or Gate Instantiation,
an instance is represented by the module or
gate name, followed by the instance name.
interactive mode The simulation mode in
which you choose on-screen options and
buttons, and execute menu commands,
with the keyboard or mouse.
ISP see in-system programmability.
J
Jam File (.jam) An ASCII file (with the
extension .jam) in the Jam device
programming and test language that stores
programming data for programming,
verifying, and blank-checking one or more
in-system programmable devices in a
JTAG chain. Jam files are use in embedded
processor-type programming
environments. AlteraÕs MAX 7000S and
MAX 9000 devices can be programmed
with Jam files. The JTAG chain can contain
any other device that complies with the
IEEE 1149.1 JTAG specification, including
FLEX 10K, FLEX 6000, and some FLEX 8000
devices.
You can generate Jam files with the Create
Jam or SVF File command (File menu) in
the Programmer or the Compiler.
JCF see JTAG Chain File.
JEDEC File (.jed) An ASCII file (with the
extension .jed) that contains programming
information. JEDEC Files provide an
industry-standard format for transferring
information between a data preparation
system and a logic device programmer.
The MAX+PLUS II Compiler automatically
generates JEDEC Files for all Classic
devices and the EPM5032 device during
compilation.
The MAX+PLUS II Programmer can use a
JEDEC File created with MAX+PLUS II,
MAX+PLUS (DOS), A+PLUS, or PLDshell
Plus to program the Altera devices listed
above. The Programmer can also
optionally save programming data plus
functional test vectors in JEDEC File
format.
JTAG boundary-scan testing Testing that
isolates a deviceÕs internal circuitry from its
I/O circuitry. This testing is made possible
by the Joint Test Action Group (JTAG)
Boundary-Scan Test (BST) architecture that
is available in all FLEX 10K devices; all
FLEX 8000 devices except the EPF8452A
and EPF81188A; all FLEX 6000 devices; all
MAX 9000 devices; and all MAX 7000S
devices except the EPM7064S. Serial data is
shifted into boundary-scan cells in the
device; observed data is shifted out and
externally compared to expected results.
Boundary-scan testing offers efficient PC
board testing, providing an electronic
substitute for the traditional Òbed of nailsÓ
test fixture.
The full or partial JTAG BST architecture in
all FLEX 10K, MAX 9000, and MAX 7000S
devices also supports in-system multi-
device JTAG chain device programming
and configuration.
JTAG chain see multi-device JTAG chain.
JTAG Chain File (.jcf) An ASCII file (with
the extension .jcf) that stores device name,
device order, and optional programming
file name information for use in
programming or configuring one or more
devices in a JTAG chain. A JCF saves
information entered with the Compiler or
ProgrammerÕs Create Jam or SVF File
81_GSBOOK.fm5 Page 315 Tuesday, October 14, 1997 4:04 PM