Unit installation

MAX+PLUS II Getting Started
316 Altera Corporation
command (File menu) or Multi-Device
JTAG Chain Setup command (JTAG
menu).
K
keyword Words that are reserved for
implementing syntax in files used as inputs
to MAX+PLUS II, including AHDL Text
Design Files (.tdf), Assignment &
Configuration Files (.acf), Command Files
(.cmd), EDIF Command Files (.edc),
Library Mapping Files (.lmf), VHDL
Design Files (.vhd), Verilog Design
Files (.v) and Vector Files (.vec). For
example, the keyword OF cannot be used
as an unquoted symbolic name in an
AHDL file.
L
LAB see Logic Array Block.
latch A level-sensitive clocked storage
unit that stores a single bit of data. A high-
to-low transition on the Latch Enable signal
fixes the contents of the latch at the value of
the data input until the next low-to-high
transition of the Latch Enable.
Latch Enable A level-sensitive signal that
controls a latch. When it is high, the input
flows through the output; when it is low,
the output holds its last value.
LC see logic cell.
least significant bit (LSB) The bit of a
binary number that contributes the
smallest quantity to the value of that
number, i.e., the last member in a bus or
group name. For example, the LSB for a bus
or group named a[31..0] is a[0] (or
a0).
Library Mapping File (.lmf) An ASCII text
file (with the extension .lmf) used to map
cells in EDIF Input Files (.edf) or symbols
in OrCAD Schematic Files (.sch) to
corresponding MAX+PLUS II primitives,
megafunctions, and macrofunctions.
Library of Parameterized Modules (LPM)
A technology-independent library of logic
functions that are parameterized to achieve
scalability and adaptability. Altera has
implemented parameterized modules (also
called Òparameterized functionsÓ) from
LPM version 2.1.0 that offer architecture-
independent design entry for all
MAX+PLUS II-supported devices. The
MAX+PLUS II Compiler includes built-in
compilation support for LPM functions
used in schematic, AHDL, VHDL, Verilog
HDL, and EDIF input files.
LMF see Library Mapping File.
Load An input signal that loads data into
a register. A synchronous Load signal
loads data on each rising or falling Clock
edge. An asynchronous Load signal loads
data regardless of the Clock signal.
local routing A resource assignment
available for FLEX 6000 devices that
assigns a fan-out of a node to be placed in
logic cell in the same LAB as the node or in
an adjacent LAB to the node. Local routing
is also available between a node that is
placed in a logic cell in an LAB on the
periphery of a device and the output pin
that it feeds. Local routing assignments
ensure that the signals are connected with
shared local interconnect, which is the
fastest interconnect available. Therefore,
you can maximize your projectÕs
performance by connecting logic on a
speed-critical path with local routing.
81_GSBOOK.fm5 Page 316 Tuesday, October 14, 1997 4:04 PM