Unit installation

MAX+PLUS II Getting Started
324 Altera Corporation
net ID number see symbol ID number.
network A group of interconnected node
and/or bus lines, including nodes or buses
that are connected by name only.
node A node represents a wire carrying a
signal that travels between different logical
components of a design file. In Verilog
HDL, nodes are called Ònets.Ó
In the Graphic Editor files, nodes are
represented as lines; in text files, they are
symbolic names; in Waveform Editor files,
they are waveforms.
Node Database File (.ndb) A file that
contains the database of project node
names, which supports resource and probe
assignment edits with Assign menu
commands and the Floorplan Editor. The
Compiler Netlist Extractor and Database
Builder modules of the Compiler generate
a Node Database File for a project during
project processing.
1 1. If you turn on the CompilerÕs
Preserve All Node Name
Synonyms command
(Processing menu) before
compilation, this file will not
contain all possible forms of the
project node names.
2. If you accidentally delete this
file, you must recompile the
project before you can use most
Assign menu commands and
Floorplan Editor functions. In
addition, only pins are visible in
the Floorplan Editor if a Node
Database File is created with the
Project Save & Check command
(File menu): a full compilation is
required to make buried nodes
visible in the Floorplan Editor.
node or net name The name given to a
signal in a design file. A node or net name
can contain up to 32 of the following name
characters: A to Z, a to z, 0 to 9, slash (/),
dash (-), and underscore (_). Hierarchical
node names can contain 128 characters,
including vertical bar (|), colon (:), and
period (.). Case is not significant.
Some restrictions apply to names in VHDL
Design Files (.vhd), Verilog Design
Files (.v), and unquoted port and symbolic
names in AHDL Text Design Files (.tdf).
node type The type of logic that drives a
node or group in a Waveform Design File
(.wdf) or Vector File (.vec). Four logic types
are defined:
VHDL names No slash (/) or dash (-) is
permitted. The name must
start with a letter, cannot
end with an underscore
(_), and cannot contain two
underscores (_ _) in a row.
VHDL keywords cannot be
used.
ACF names Names that contain slash
(/), dash (-), vertical bar
(|), colon (:), and/or
period (.) characters must
be enclosed in double
quotation marks (").
Item: Name Character
Exception:
Type: Meaning:
INPUT Node or group is driven by an
input pin.
81_GSBOOK.fm5 Page 324 Tuesday, October 14, 1997 4:04 PM