Unit installation

MAX+PLUS II Getting Started
328 Altera Corporation
Declarations, Module Instantiations, and
Gate Instantiations of Verilog Design
Files (.v).
pinstub name A symbolic name that
identifies an input or output of a logic
function.
In the Symbol Editor, the ÒvisibleÓ pinstub
name appears both inside and outside of
the symbol. This ÒvisibleÓ pinstub name
can be an abbreviation or an alias for the
ÒfullÓ pinstub name, which represents the
full name of the original input, output, or
bidirectional pin in a mega- or
macrofunction design file or primitive
Function Prototype.
You can specify whether or not to display
the ÒvisibleÓ pinstub name in a Graphic
Editor file when you create a pinstub in the
Symbol Editor. The use or non-use of a
particular pinstub (and hence its visibility)
can be customized when you edit a symbol
instance in the Graphic Editor with Edit
Ports/Parameters (Symbol menu).
Pinstubs in Graphic Editor files are
synonymous with ports in AHDL Function
Prototypes and VHDL Component
Declarations. They are also listed in the
Subdesign Sections of lower-level Text
Design Files (.tdf); in Entity Declarations of
lower-level VHDL Design Files (.vhd); and
in Module Declarations, Module
Instantiations, and Gate Instantiations of
Verilog Design Files (.v).
PLF see Programmer Log File.
PLS-ES A PC-based MAX+PLUS II
development system, which is
automatically provided on a site license
when you purchase any PC-based
MAX+PLUS II development system.
PLS-ES development systems include the
following MAX+PLUS II applications and
features:
■ Hierarchy Display
■ Graphic, Symbol, and Text Editors
■ Compilation support for Classic,
MAX 5000, MAX 7000/7000E/7000S,
EPF8282, EPF8452, EPM9320, and
EPF10K10 devices
■ EDIF Interfaces (input and output)
■ Verilog HDL and VHDL output
■ Timing Analyzer
■ Message Processor
■ Programmer
POF see Programmer Object File.
port A symbolic name that represents an
input or output of a primitive or of a design
file.
In AHDL, a port name in the Subdesign
Section represents an input or output of the
current file. This port name also appears in
the Function Prototype for the function.
When an instance of a primitive or lower-
level design file is implemented with an
Instance Declaration or an in-line
reference, its ports are used to connect it to
other functions in the TDF. After an
instance is declared, its inputs and outputs
are expressed as names in the format
<instance name>.<port name> in the Logic
Section. When an in-line reference is used,
either named port association or positional
port association can be used to connect the
functionÕs ports to other functions in the
TDF.
In VHDL, a port name in the Entity
Declaration represents an input or output
of the current file. When an instance of a
primitive or lower-level design file is
implemented with a Component
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