Unit installation

Glossary
Altera Corporation 329
Glossary
Glossary
Instantiation, its ports are connected to
signals with Port Map Aspects.
In Verilog HDL, a port in a Module
Declaration represents an input or output
of the current file. When an instance of a
lower-level design file is implemented
with a Module Instantiation, its ports are
connected by order or by name to the
Module Declaration ports of the module
being instantiated. Similarly, when a
primitive is implemented with a Module
Instantiation, its ports are used to connect it
by order of other functions in the file.
Verilog HDL gate primitives also contain
ports (called ÔterminalsÓ); when a gate
primitive is implemented with a Gate
Instantiation, its terminals are connected
by order to the terminals of the gate being
instantiated.
A port name in an AHDL Subdesign
Section, VHDL Entity Declaration, or
Verilog HDL Module or Gate Declaration
is synonymous with a pin name in a
Graphic Design File (.gdf) or Waveform
Design File (.wdf). A port name that is
appended to an instance name is
synonymous with the full pinstub name in
an instance of a symbol in a Graphic Editor
file.
Preset An input signal that
asynchronously sets the output of a
register to a logic high (1), regardless of
other inputs.
primitive One of the basic functional
blocks used to design circuits with
MAX+PLUS II software. Primitives are
used in Graphic Design Files (.gdf), AHDL
Text Design Files (.tdf), VHDL Design Files
(.vhd), and Verilog Design Files (.v).
Graphic Editor primitives include buffers,
flipflops, a latch, input and output
primitives, and logic primitives. Primitive
symbols for Graphic Editor files are
provided in the \maxplus2\max2lib\
prim directory created during installation.
AHDL, VHDL, and Verilog HDL
primitives, which include buffers,
flipflops, and a latch, are a subset of the
primitive symbols used in Graphic Editor
files. Other functions are represented by
logical operators, ports, and other
constructs. Function Prototypes for AHDL
primitives are built into the MAX+PLUS II
software; Component Declarations for
VHDL primitives are provided in the
maxplus2 package in the \maxplus2\
max2vhdlnn\altera directory, where nn is
Ò87Ó or Ò93Ó.
1 On a UNIX workstation, the
maxplus2 directory is a subdirectory
of the /usr directory.
primitive array A single primitive that is
connected to two or more buses in order to
represent multiple primitives.
probe A unique name assigned to any
node, e.g., the input or output of a
primitive, megafunction, or macrofunction
which can be used instead of the full
hierarchical node name throughout
MAX+PLUS II. A probe name thus
provides a short name to identify a node.
product term Two or more factors in a
Boolean expression combined with an AND
operator constitute a product term, where
ÒproductÓ means Òlogic product.Ó
81_GSBOOK.fm5 Page 329 Tuesday, October 14, 1997 4:04 PM