Unit installation

MAX+PLUS II Getting Started
332 Altera Corporation
resource assignment An assignment of a
logic function in a project to a particular
pin, logic cell, I/O cell, embedded cell,
logic array block (LAB), embedded array
block (EAB), row, column, or chip. This
type of resource assignment assigns a logic
function to a physical resource in a device.
A resource assignment can also consist of a
clique, logic option, connected pin, timing
requirement, or local routing assignment to
a particular logic function in a project. This
type of resource assignment assigns a
compilation resource to a logic function.
row A horizontal line of LABs connected
by a row FastTrack Interconnect path in a
FLEX 6000, FLEX 8000, FLEX 10K, or
MAX 9000 device.
RS-232 port see COM port.
S
SCF see Simulator Channel File.
SDF Output File see Standard Delay
Format Output File.
secondary input The Clock, Preset,
synchronous and asynchronous Reset
(Clear), and synchronous and
asynchronous Load inputs to a register or a
state machine in a design file.
Security Bit A bit that prevents an
EPROM- or EEPROM-based Altera device
from being interrogated. This bit also
prevents EPROM-based Altera devices
from being inadvertently reprogrammed.
The Security Bit can be turned on or off for
each device in a project, or for the entire
project.
segment see memory segment.
Serial Bitstream File (.sbf) An ASCII file
(with the extension .sbf) that contains the
data for configuring a FLEX 6000,
FLEX 8000, or FLEX 10K device with the
BitBlaster from a system prompt. This file
can be generated with the Combine
Programming Files command (File menu)
in the Compiler or the Simulator.
Serial Vector Format File (.svf) An ASCII
file (with the extension .svf) that stores
programming data for programming one
or more fixed algorithm devices in
Automated Test Equipment (ATE)-type
programming environments. AlteraÕs
MAX 7000S and MAX 9000 devices can be
programmed with SVF Files. The JTAG
chain can contain any other device that
complies with the IEEE 1149.1 JTAG
specification, including FLEX 10K,
FLEX 6000, and some FLEX 8000 devices.
You can create SVF Files with the Create
Jam or SVF File command (File menu) in
the Programmer or the Compiler.
setup time On a flipflop, the setup time is
the minimum time interval between the
application of a signal at the input pin that
feeds the data or Clock Enable input and a
low-to-high transition at the input pin that
feeds the Clock input of the flipflop or the
Latch Enable input of the latch.
On a latch, the setup time is the minimum
time interval between the application of a
signal at the input pin that feeds the data
input of a latch and a low-to-high
transition at the input pin that feeds the
Latch Enable input of the latch. (Setup and
hold time analysis for latches is available
only for MAX 5000 devices. In other device
families, latches are implemented using
combinatorial logic with feedback.)
81_GSBOOK.fm5 Page 332 Tuesday, October 14, 1997 4:04 PM