Unit installation

Glossary
Altera Corporation 333
Glossary
Glossary
On an asynchronous RAM block, the setup
time is the minimum time interval between
the application of a signal at the input pin
that feeds the data or address inputs and a
low-to-high or high-to-low transition at the
input pin that feeds the Write Enable input
of the RAM block.
Internal setup times for flipflops, latches,
and asynchronous RAM, which are not
user-defined, similarly constrain signals
that are generated within the device.
shared local interconnect Dedicated
connection paths on FLEX 6000 devices
that allow signals to travel quickly between
logic cells in the same LAB or adjacent
LABs, or between logic cells on the
periphery of the device and I/O pins.
Shared local interconnect is the fastest
interconnect available in FLEX 6000
devices.
SIF see Simulator Initialization File.
Simulator Channel File (.scf) A graphical
waveform file (with the extension .scf) that
is both an input and an output to the
Simulator. This file contains a waveform
representation of the vector values on the
input nodes that drive simulation, as well
as the buried and output nodes to be
simulated. Waveforms in the file represent
high (1), low (0), high-impedance (Z), and
undefined (X) logic levels.
An SCF can be created and viewed in the
Waveform Editor; the Simulator also
automatically creates and updates an SCF
during simulation. An SCF can also be
used to provide the vector inputs for
functional testing in the Programmer.
Simulator Initialization File (.sif) A file
(with the extension .sif) that saves all node,
group, and memory values, including
initialized values entered with the
SimulatorÕs Initialize Nodes/Groups and
Initialize Memory commands (Initialize
menu) or the Command File (.cmd) GROUP
INIT and NODE INIT commands. The SIF
allows you to reuse a previously saved set
of node and group values.
Simulator Netlist File (.snf) A binary file
(with the extension .snf) that contains the
data for functional simulation, timing
simulation or timing analysis, or linked
multi-device simulation. Three optional
Compiler modules create the different
types of SNFs that contain the information
required for different simulation modes
and/or timing analysis:
■ The Timing SNF Extractor generates a
timing SNF that contains all data
required for timing simulation and full
timing analysis.
■ The Functional SNF Extractor
generates a functional SNF that
contains all data required for
functional simulation.
■ The Linked SNF Extractor generates a
linked SNF that combines timing and/
or functional data from the timing,
functional, and/or linked SNFs for
other previously compiled projects. If
all of the combined SNFs are timing
SNFs, a linked SNF can also be used for
full timing analysis.
Only one type of SNF can exist at any
particular time for the same project.
single-range group (or bus) name The
name of a group (or bus) of up to 256
nodes, consisting of an identifier with up to
32 name characters, followed by a range of
numbers or arithmetic expressions in
brackets. The start and end of the range are
81_GSBOOK.fm5 Page 333 Tuesday, October 14, 1997 4:04 PM