Unit installation

MAX+PLUS II Getting Started
339 Altera Corporation
.
In MAX 7000E devices, the Turbo Bit option
and the Slow Slew Rate option on output
pins are controlled by a single bit.
Therefore, only one of these options can be
turned on on an output pin at any one time.
If both options are turned on or if both
options are turned off, the Compiler uses
the Slow Slew Rate setting and ignores the
Turbo Bit setting. On input pins and buried
logic cells, the Compiler uses the Turbo Bit
setting and ignores the Slow Slew Rate
setting.
two’s complement A system of
representing binary numbers in which the
negative of a number is equal to its inverse
plus 1. Arithmetic operators in AHDL
assume that groups they operate on are a
twoÕs complement binary number. In
VHDL, you must declare a twoÕs
complement binary number with a signed
data type.
U
user libraries One or more directories that
contain your own megafunctions,
macrofunctions, Symbol Files (.sym),
AHDL Include Files (.inc), or precompiled,
user-defined VHDL packages.
The Compiler automatically searches for
these user-specified libraries when it
compiles a project. The CompilerÕs VHDL
Netlist Settings command (Interfaces
menu) specifies VHDL design libraries for
the current project. You can specify which
directories contain your other user libraries
with the User Libraries command
(Options menu) in any MAX+PLUS II
application.
V
variable A name that represents a node. In
AHDL, a variable can also represent a state
machine or an instance of a primitive,
megafunction, or macrofunction and is
declared in the Variable Section. In VHDL,
variables have a single current value, and
are declared and used only in processes
and subprograms. A VHDL variable is
declared with a Variable Declaration; the
value of a variable can be modified with a
Variable Assignment Statement.
VCC A high-level input voltage
represented as a high (1) logic level in
binary group values.
In an AHDL Text Design File (.tdf), VCC is
a predefined constant and keyword, and
the default active node value. In a VHDL
Design File (.vhd), VCC is represented
by'1'. In a Verilog Design File (.v), VCC is
represented by 1. In a Graphic Editor file,
VCC is a primitive symbol. VCC is
represented as a high (1) logic level in the
Simulator and Waveform Editor.
vector A vector specifies the logic levels
for an individual node within a project. The
Altera Device
Family:
Turbo Bit Availability:
Classic Applies to the entire
device (specified as a
device option)
MAX 5000 Not available
MAX 7000 Applies to individual logic
cells within a device
(specified as a logic option)
MAX 9000 Applies to individual logic
cells within a device
(specified as a logic option)
FLEX 6000 Not available
FLEX 8000 Not available
FLEX 10K Not available
81_GSBOOK.fm5 Page 339 Tuesday, October 14, 1997 4:04 PM