Unit installation

MAX+PLUS II Getting Started
340 Altera Corporation
Simulator uses vectors to simulate the
behavior of the project; the Programmer
and Simulator use vectors for functional
testing.
Vectors for simulation and functional can
be defined in Vector Files (.vec) or
Simulator Channel Files (.scf). Functional
testing vectors can also be stored in
programming files.
Vectors for design entry can be defined in a
Waveform Design File (.wdf).
Vector File (.vec) An ASCII file (with the
extension .vec) that contains vectors that
specify the logic levels of input nodes in a
project. The Simulator uses this file to test
the logical operation of the project; the
Programmer and Simulator can also use a
Vector File for functional testing.
In addition, a Vector File can also be
converted into a Waveform Design File
(.wdf) for design entry.
Verilog Design File (.v) A Verilog HDL
File (with the extension .v) created with the
MAX+PLUS II Text Editor or any other
standard text editor. Verilog Design Files
can be compiled with the MAX+PLUS II
Compiler.
Verilog HDL A Hardware Description
Language (HDL).
You can create a Verilog Design File (.v)
with the MAX+PLUS II Text Editor or any
standard text editor and compile it directly
with MAX+PLUS II.
You can also generate an EDIF 2 0 0 or 3 0 0
netlist file from a Verilog HDL design that
has been processed with a Verilog HDL
synthesis tool, then import the file into
MAX+PLUS II as an EDIF Input File (.edf).
In addition, you can directly process a
Verilog Design File (.v) in MAX+PLUS II
with Synopsys tools if you turn on the
Synopsys Compiler command (Interfaces
menu). The MAX+PLUS II Compiler can
also generate a Verilog Output File (.vo)
that contains functional and timing
information for simulation with a standard
Verilog HDL simulator.
Verilog Output File (.vo) A Verilog
Hardware Description Language (HDL)
standard netlist file (with the extension .vo)
that is generated by the Verilog Netlist
Writer module of the Compiler. This file
can be exported to an industry-standard
Verilog HDL simulator for simulation. A
Verilog Output File cannot be compiled
with the MAX+PLUS II Compiler.
VHDL Very High Speed Integrated Circuit
(VHSIC) Hardware Description Language.
You can create a VHDL Design File (.vhd)
with the MAX+PLUS II Text Editor or any
standard text editor and compile it directly
with MAX+PLUS II. You can also generate
an EDIF 2 0 0 or 3 0 0 netlist file from a
VHDL design that has been processed with
a VHDL synthesis tool, then import the file
into MAX+PLUS II as an EDIF Input File
(.edf). The MAX+PLUS II Compiler can
also generate a VHDL Output File (.vho)
that contains functional and timing
information for simulation with a standard
VHDL simulator, and a VHDL Memory
Model Output File (.vmo) that contains
simulation models for a RAM or ROM
block.
VHDL Design File (.vhd) An ASCII text file
(with the extension .vhd) written in VHDL.
VHDL Design Files can be compiled by the
MAX+PLUS II Compiler.
81_GSBOOK.fm5 Page 340 Tuesday, October 14, 1997 4:04 PM