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Application Report

SLAA154 – October 2002

Interfacing the TLV320AIC12/13/14/15 Codec to the

TMS320C5402™ DSP

Bolanle Onodipe High Performance Analog Products

ABSTRACT

This application report presents the process of interfacing of the TLV320AIC12/13/14/15

voice-band codec with the TMS320C5402™ DSP. It presents the hardware configuration

and the software driver for a two-device cascade (single master and single slave)

configuration mode. The design can be considered as an application example, a test tool,

or a startup platform for developing and using the codec/DSP system.

Contents

1 Introduction...................................................................................................................................2

2 Hardware System..........................................................................................................................3

2.1 Basic Stand-Alone Master Codec/DSP Interface.....................................................................3

2.2 Basic Two-AIC12 Cascade Codec/DSP Interface ...................................................................4

2.3 Codec/C5402™ DSP Starter Kit System.................................................................................4

3 Software Interface.........................................................................................................................4

3.1 Codec Control Register Initialization .......................................................................................4

3.2 Analog Interface......................................................................................................................6

3.2.1 Analog Inputs ..............................................................................................................6

3.2.2 Analog Outputs............................................................................................................6

3.3 Digital Interface.......................................................................................................................6

3.4 Interface Data Format .............................................................................................................7

3.5 Control Frame Data Format ....................................................................................................9

4 Design Issues..............................................................................................................................10

5 Test Procedure for AIC12...........................................................................................................11

5.1 TLV320AIC Development Platform Board Setup...................................................................11

5.2 SYNC RESET Synchronization Test .......................................................................................11

5.3 AIC12 EVM Board.................................................................................................................12

5.4 AC Test.................................................................................................................................13

6 References ..................................................................................................................................13

Figures

Figure 1. Typical AIC12/C54xx™ DSP Digital Interface, Stand-Alone Master Operation...................3

Figure 2. Typical AIC12/C54xx™ DSP Digital Interface, Two-AIC12 Cascade Mode ........................5

Figure 3. Master / Slave Communication in Programming Mode.......................................................7

Figure 4. Master / Slave Communication in Continuous Mode ..........................................................8

Figure 5. Data Frame Format............................................................................................................8

Figure 6. Control Frame Data Format................................................................................................9

TMS320C5402, TMS320C54xx, TMS320C28xx, and TMS320C6xxx are trademarks of Texas Instruments. All trademarks are

the property of their respective owners.

Summary of content (15 pages)

PAGE 1
Application Report SLAA154 – October 2002 Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP Bolanle Onodipe High Performance Analog Products ABSTRACT This application report presents the process of interfacing of the TLV320AIC12/13/14/15 voice-band codec with the TMS320C5402™ DSP. It presents the hardware configuration and the software driver for a two-device cascade (single master and single slave) configuration mode.
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SLAA154 Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. 1 Tables Control Register Address Chart........................................................................................10 Test Point Voltage Levels.................................................................................................11 Development Platform Jumpers .......................................................................................11 AIC12 EVM Board Jumpers .................................................
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SLAA154 An AIC12 device is defined a master or a slave on the basis of the origin of the FS and SCLK. The AIC12 is a master if the FS and SCLK are generated by the AIC12 and both signals are the outputs from the codec to the host processor or other codec devices. Otherwise, if the two signals are inputs to the codec, the AIC12 is called a slave. Moreover, if only one AIC12 interfaces with a serial port of the host processor, it is said to be operating in the stand-alone mode.
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SLAA154 In the Figure 1, note that the reset and power-down signals must be synchronized to the main clock (MCLK) of the codec. For more information see reference [5]. Also note that the maximum frequency of MCLK is 100MHz 2.2 Basic Two-AIC12 Cascade Codec/DSP Interface The typical circuit for the two AIC12 devices in cascade operation mode is given in Figure 2. As in the case of the stand-alone operation, the reset and power-down signals must be synchronized to the main clock (MCLK).
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Figure 2.
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SLAA154 3.2 Analog Interface The AIC12 device has a full complement of analog input and output terminals that facilitate modern digital telephony and voice communication. The AIC12 codec has three software selectable analog inputs and three programmable outputs. The selection of these analog inputs and outputs is determined by the programmed statuses of the D1 and D2 bits, and the D7, D3, and D4 bits of the configuration register CR6 respectively. 3.2.
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SLAA154 The following equations determine the respective frequencies: 3.4 • FS (frame synchronization frequency) = MCLK / (16 * M * N * P). Reference [1] provides a complete description of the programmable M, N, and P parameters. These parameters are programmed through control register four (CR4). To specify the value for M, bit D7 of CR4 must be set, and the value specified in bit locations D0 through D6 are assigned to it.
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SLAA154 Within each frame, the data frame for each device is transmitted first in one block, immediately followed by the corresponding control frame block. This process is repeated indefinitely, until the data frame select bit, bit D6 of CR1 is set, implying a continuous data transfer request. Subsequently, the serial shift clock rate is automatically halved, and the control frame block is dropped—see Figure 4.
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SLAA154 3.5 Control Frame Data Format The codec’s control frame data is composed of various types of data, depending on the direction and the read/write mode of operation.
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SLAA154 Table 1. Control Register Address Chart Register Address D15 D14 D13 Register Name 0 0 0 0 No Operation 1 0 0 1 Control Register 1 (CR1) 2 0 1 0 Control Register 2 (CR2) 3 0 1 1 Control Register 3 (CR3) 4 1 0 0 Control Register 4 (CR4) 5 1 0 1 Control Register 5 (CR5) 6 1 1 0 Control Register 6 (CR6) 2. In the read mode, bit D12 of the DIN control data stream is set, while in the write mode, the D12 bit is cleared. 3.
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SLAA154 5 Test Procedure for AIC12. 5.1 TLV320AIC Development Platform Board Setup 1. Select the 3.3 V source from the DSP (DSP_3.3VDC), by setting the jumper W1 for 1-2. 2. Plugging the TLV320AIC development platform to the DSP DSK through the common connector turns on the two yellow LEDs, D1 and D2. 3. Confirm that the digital and analog power sources, and grounds are properly isolated. 4. Confirm the following voltage levels on the listed test points, and J3 pins. Table 2.
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SLAA154 With the scope in the single trigger mode, and set the scope sync to trigger on the rising edge of the TP12 signal, press the reset push button on the development platform. Confirm that the rising edge of SYNC RESET occurs on the rising edge of MCLK. Then set the scope sync to trigger on the falling edge of the TP12 signal; again press the reset push button on the development platform. Confirm that the falling edge of SYNC RESET also occurs on the rising edge of MCLK. 5.
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SLAA154 5.4 AC Test With the jumper settings as described above, apply a periodic signal from a function generator to J3 and J5 input terminals of the AIC12 EVM board. The frequency of the applied signal must be less than 7 kHz, since the sampling frequency of the codec is 15.625 kHz. Compile and load the AIC12SW_C.pjt project program onto the DSK. This software programs the codec to operate in the continuous mode—set M = 20, N = 5 and P = 2.
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SLAA154 14 [11] TMS320C54x DSP Mnemonic Instruction Set, Reference Set Volume 2 (SPRU172B) [12] TMS320C54x Assembly Language Tools, user’s guide (SPRU102D) [13] TMS320C54x Optimizing C Compiler, user’s guide (SPRU103D) [14] TMS320C54x DSP Applications Guide, Reference Set Volume 4 (SPRU173) Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402™ DSP
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