Datasheet

ManualsBrandsAmyko ManualsDRAMDRAM 128MB 5.4ns TSOP-II

AS4C8M16SA

Confidential

Rev. 2.2 Mar /2014

128M - 8M x 16 bit Synchronous DRAM (SDRAM)

Confidential (Rev. 2.2, March 2014)

Features



Fast access time from clock: 5/5.4 ns



Fast clock rate: 166/143 MHz



Fully synchronous operation



Internal pipelined architecture



2M word x 16-bit x 4-bank



Programmable Mode registers

- CAS Latency: 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: Sequential or Interleaved

- Burst stop function



Operating temperature range

- Commercial (0 ~ 70°C)

- Industrial (-40 ~ 85°C)



Auto Refresh and Self Refresh



4096 refresh cycles/64ms



CKE power down mode



Single +3.3V 

0.3V power supply



Interface: LVTTL



54-pin 400 mil plastic TSOP II package



54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package

All parts ROHS Compliant

Overview

The 128Mb SDRAM is a high-speed CMOS

synchronous DRAM containing 128 Mbits. It is

internally configured as 4 Banks of 2M word x 16

DRAM with a synchronous interface (all signals are

registered on the positive edge of the clock signal,

CLK). Read and write accesses to the SDRAM are

burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with

the registration of a BankActivate command which

is then followed by a Read or Write command.

The SDRAM provides for programmable Read

or Write burst lengths of 1, 2, 4, 8, or full page, with

a burst termination option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence. The refresh functions, either Auto or Self

Refresh are easy to use.

By having a programmable mode register, the

system can choose the most suitable modes to

maximize its performance. These devices are well

suited for applications requiring high memory

bandwidth and particularly well suited to high

performance PC applications.

Table 1. Key Specifications

AS4C16M16S

-6/7

tCK3

Clock Cycle time (min.)

6/7 ns

tAC3

Access time from CLK (max.)

5.4/5.4 ns

tRAS

Row Active time (min.)

42/42 ns

tRC

Row Cycle time (min.)

60/63 ns

Table 2. Ordering Information

Part Number

Frequency

Package

AS4C8M16SA-7TCN

143 MHz

54 pin TSOP II

AS4C8M16SA-6TCN

166 MHz

54 pin TSOP II

AS4C8M16SA-6TIN

166 MHz

54 pin TSOP II

AS4C8M16SA-6BIN

166 MHz

54 ball TFBGA

AS4C8M16SA-7BCN

143 MHz

54 ball TFBGA

T : indicates TSOP II package

B : indicates TFBGA package

N : indicates Pb free and Halogen free – ROHS compliant parts

C: Commercial I: Industrial

Summary of content (54 pages)

PAGE 1
AS4C8M16SA 128M - 8M x 16 bit Synchronous DRAM (SDRAM) Confidential (Rev. 2.2, March 2014) Features Overview Fast access time from clock: 5/5.
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AS4C8M16SA Figure 1. Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Figure 1.
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AS4C8M16SA Figure 2. Block Diagram CLOCK BUFFER Row Decoder CLK CKE 2M x 16 CELL ARRAY (BANK #A) Column Decoder COMMAND DECODER DQ Buffer CONTROL SIGNAL GENERATOR DQ0 ~ CS# RAS# CAS# WE# DQ15 A10/AP COLUMN COUNTER MODE REGISTER A9 A11 BA0 BA1 2M x 16 CELL ARRAY (BANK #B) Column Decoder ADDRESS BUFFER Row Decoder ~ A0 Row Decoder LDQM, UDQM REFRESH COUNTER 2M x 16 CELL ARRAY (BANK #C) Row Decoder Column Decoder 2M x 16 CELL ARRAY (BANK #D) Column Decoder Confidential 3 Rev. 2.
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AS4C8M16SA Pin Descriptions Table 3. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
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AS4C8M16SA WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. LDQM, UDQM Input Data Input/Output Mask: Controls output buffers in read mode and masks DQ0-DQ15 Input / Output NC/RFU - VDDQ Supply Input data in write mode.
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AS4C8M16SA Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4 shows the truth table for the operation commands. Table 4.
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AS4C8M16SA Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD (min.) from the time of bank activation.
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AS4C8M16SA T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP CAS# Latency=2 tCK2, DQ DOUT A0 CAS# Latency=3 tCK3, DQ NOP NOP NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP NOP NOP DOUT A3 Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers).
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AS4C8M16SA T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 CAS# Latency=2 tCK2, DQ Must be Hi-Z before the Write Command Don’t Care Figure 7.
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AS4C8M16SA of {tRP (min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 Write command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD (min.) before the Write command is issued.
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AS4C8M16SA T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A READ B CAS# Latency=2 tCK2, DQ DIN A0 don’t care CAS# Latency=3 tCK3, DQ DIN A0 don’t care NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care NOP NOP NOP DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12.
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AS4C8M16SA T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CLK COMMAND Bank A Activate NOP NOP WRITE A Auto Precharge NOP NOP NOP NOP Bank A Activate NOP tDAL DQ DIN A0 DIN A1 tDAL=tWR+tRP Begin AutoPrecharge Bank can be reactivated at completion of tDAL Figure 14. Burst Write with Auto-Precharge (Burst Length = 2) 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.
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AS4C8M16SA T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE tMRD CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11 DQM DQ tRP Hi-Z PrechargeAll Mode Register Set Command Don’t Care Any Command Figure 15. Mode Register Set Cycle  Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. Table 6.
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AS4C8M16SA  Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. Table 7. Burst Type Field  A3 Burst Type 0 Sequential 1 Interleave Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 8.
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AS4C8M16SA Table 10. Test Mode Field A8 A7 Test Mode 0 0 normal mode 0 1 Vendor Use Only 1 X Vendor Use Only  Write Burst Length (A9) This bit is used to select the write burst mode. When the A9 bit is "0", the Burst-Read-Burst-Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected. Table 11. Write Burst Length A9 Write Burst Mode 0 Burst-Read-Burst-Write 1 Burst-Read-Single-Write Note: A10 and BA should stay “L” during mode set cycle.
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AS4C8M16SA 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command.
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AS4C8M16SA Table 12. Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature Rating Unit Note -6/7 -1.0 ~ 4.6 V 1 -1.0 ~ 4.6 V 1 Commercial 0 ~ 70 °C 1 Industrial -40 ~ 85 °C 1 TSTG Storage Temperature -55 ~ 125 °C 1 TSOLDER Soldering Temperature (10 second) 260 °C 1 PD Power Dissipation 1 W 1 IOS Short Circuit Output Current 50 mA 1 Table 13. Recommended D.C.
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AS4C8M16SA Table 15. D.C. Characteristics (VDD = 3.3V  0.
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AS4C8M16SA Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8) Symbol tRC -6 A.C. Parameter Max. Min Max.
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AS4C8M16SA Table 17. LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50  1.2k Output Output 30pF Z0= 50  30pF 870 Figure 18.1 LVTTL D.C. Test Load (A) Figure 18.2 LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL.
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AS4C8M16SA Timing Waveforms Figure 19.
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AS4C8M16SA Figure 20.
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AS4C8M16SA Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx tRP tRC tRC CAx tRCD DQM DQ Ax0 Precharge All Command Auto Refresh Command Auto Refresh Command Activate Command Bank A Ax1 Read Command Bank A Don’t Care Confidential 23 Rev. 2.
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AS4C8M16SA Figure 22.
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AS4C8M16SA Figure 23. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 CLK *Note 1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 *Note 2 CKE tXSR *Note 5 *Note 3,4 *Note 8 tPDE tIS tIH *Note 6 tIS CS# *Note 7 RAS# *Note 9 CAS# WE# BA0,1 A10 A0-A9, A11 DQM DQ Hi-Z Hi-Z Self Refresh Exit Self Refresh Entry Auto Refresh Don’t Care Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2.
PAGE 26
AS4C8M16SA Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 26 Rev. 2.
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AS4C8M16SA Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential 27 Rev. 2.
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AS4C8M16SA Figure 25. Clock Suspension During Burst Write (Using CKE) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 DAx3 Clock Suspend 3 Cycles Clock Suspend 2 Cycles Don’t Care 28 Rev. 2.
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AS4C8M16SA Figure 26.
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AS4C8M16SA Figure 27.1.
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AS4C8M16SA Figure 27.2.
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AS4C8M16SA Figure 28.
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AS4C8M16SA Figure 29.1.
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AS4C8M16SA Figure 29.2.
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AS4C8M16SA Figure 30.
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AS4C8M16SA Figure 31.1.
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AS4C8M16SA Figure 31.2. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Confidential Ax1 Ax2 Ax3 Read Command Bank A DAy0 DAy1 Write Command Bank A 37 DAy3 Az0 The Write Data is Masked with a Zero Clock Read Latency Command Bank A Rev. 2.
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AS4C8M16SA Figure 32.1.
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AS4C8M16SA Figure 32.2.
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AS4C8M16SA Figure 33.
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AS4C8M16SA Figure 34.1.
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AS4C8M16SA Figure 34.2.
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AS4C8M16SA Figure 35.
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AS4C8M16SA Figure 36.1.
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AS4C8M16SA Figure 36.2.
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AS4C8M16SA Figure 37.
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AS4C8M16SA Figure 38.
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AS4C8M16SA Figure 39.
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AS4C8M16SA Figure 40.
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AS4C8M16SA Figure 41.
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AS4C8M16SA Figure 42.
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AS4C8M16SA Figure 43. 54 Pin TSOP II Package Outline Drawing Information 28 HE E 0.254 54  L L1 1 27 B S Symbol A A1 A2 B C D E e HE L L1 S y θ e Min --0.002 0.035 0.010 0.004 0.87 0.395 --0.455 0.016 ----0° y Dimension in inch Nom Max ----0.039 0.014 0.006 0.875 0.400 0.031 0.463 --0.032 0.028 ----- 0.047 0.008 0.043 0.018 0.008 0.88 0.405 --0.471 0.024 ----0.004 8° C A1 A2 A D L L1 Min Dimension in mm Nom Max --0.05 0.9 0.25 0.12 22.09 10.03 --11.56 0.4 ------0° ----1.0 0.
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AS4C8M16SA Figure 44. 54 Ball TFBGA Package Outline Drawing Information A1 INDEX Bottom View TOP View Side View Symbol A A1 A2 D E D1 E1 e b F Confidential Dimension in inch Min Nom Max --0.047 0.010 0.012 0.014 -0.033 -0.311 0.315 0.319 0.311 0.315 0.319 -0.252 --0.252 --0.031 -0.016 0.018 0.020 -0.126 -53 Dimension in mm Min Nom Max --1.20 0.25 0.30 0.35 -0.85 -7.90 8.00 8.10 7.90 8.00 8.10 -6.40 --6.40 --0.80 -0.40 0.45 0.50 -3.20 -Rev. 2.
PAGE 54
AS4C8M16SA Confidential 54 Rev. 2.