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AD1854

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REV. A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

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Fax: 781/326-8703 © Analog Devices, Inc., 2000

Stereo, 96 kHz, Multibit  DAC

FUNCTIONAL BLOCK DIAGRAM

ATTEN/

MUTE

ATTEN/

MUTE

SERIAL

DATA

INTERFACE

8  F

INTERPOLATOR

MULTIBIT SIGMA-

DELTA MODULATOR

SERIAL CONTROL

INTERFACE

CLOCK

CIRCUIT

OUTPUT

BUFFER

OUTPUT

BUFFER

DAC

MULTIBIT SIGMA-

DELTA MODULATOR

VOLTAGE

REFERENCE

VOLUME

MUTE

CONTROL DATA

INPUT

DIGITAL

SUPPLY

CLOCK

96/48F

CLOCK

ANALOG

OUTPUTS

ZERO

FLAG

ANALOG

SUPPLY

DE-EMPHASISMUTE

PD/RST

SERIAL

MODE

16-/18-/20-/24-BIT

DIGITAL

DATA INPUT

AD1854

8  F

INTERPOLATOR

FEATURES

5 V Stereo Audio DAC System

Accepts 16-/18-/20-/24-Bit Data

Supports 24 Bits and 96 kHz Sample Rate

Multibit Sigma-Delta Modulator with “Perfect Differential

Linearity Restoration” for Reduced Idle Tones and

Noise Floor

Data Directed Scrambling DAC—Least Sensitive to Jitter

Differential Output for Optimum Performance

113 dB Dynamic

Range at 48 kHz Sample Rate

(AD1854KRS)

112 dB Signal-to-Noise at 48 kHz Sample Rate

(AD1854KRS)

–101 THD+N (AD1854KRS)

On-Chip Volume Control with 1024 Steps

Hardware and Software Controllable Clickless Mute

Zero Input Flag Outputs for Left and Right Channels

Digital De-Emphasis Processing

Supports 256  F

or 384  F

Master Mode Clock

Switchable Clock Doubler

Power-Down Mode Plus Soft Power-Down Mode

Flexible Serial Data Port with Right-Justified, Left-

Justified, and I

S-Compatible

28-Lead SSOP Plastic Package

APPLICATIONS

DVD, CD, Set-Top Boxes, Home Theater Systems,

Automotive Audio Systems, Sampling Musical

Keyboards, Digital Mixing Consoles, Digital Audio

Effects Processors

PRODUCT OVERVIEW

The AD1854 is a high performance, single-chip stereo, audio

DAC delivering 113 dB Dynamic Range and 112 dB SNR

(A-weighted—not muted) at 48 kHz sample rate. It is comprised

of a multibit sigma-delta modulator with dither, continuous

time analog filters and analog output drive circuitry. Other features

include an on-chip stereo attenuator and mute, programmed

through an SPI-compatible serial control port. The AD1854

is fully compatible with current DVD formats, including 96 kHz

sample frequency and 24 bits. It is also backwards compatible

by supporting 50 µs/15 µs digital de-emphasis intended for

“redbook” 44.1 kHz sample frequency playback from com-

pact discs.

The AD1854 has a very simple but very flexible serial data input

port that allows for glueless interconnection to a variety of ADCs,

DSP chips, AES/EBU receivers and sample rate converters.

The AD1854 can be configured in left-justified, I

S, and right-

justified. The AD1854 accepts serial audio data in MSB first,

twos-complement format. A power-down mode is offered to mini-

mize power consumption when the device is inactive. The AD1854

operates from a single 5 V power supply. It is fabricated on a single

monolithic integrated circuit and housed in a 28-lead SSOP

package for operation over the temperature range 0°C to 70°C.

Summary of content (12 pages)

PAGE 1
a Stereo, 96 kHz, Multibit DAC AD1854 PRODUCT OVERVIEW FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits and 96 kHz Sample Rate Multibit Sigma-Delta Modulator with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC—Least Sensitive to Jitter Differential Output for Optimum Performance 113 dB Dynamic Range at 48 kHz Sample Rate (AD1854KRS) 112 dB Signal-to-Noise at 48 kHz Sample Rate (AD1854KRS) –101 THD+N (
PAGE 2
AD1854–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO 5.0 V 25°C 12.288 MHz (256 × FS Mode) 1.0013 kHz –0.5 dB Full Scale 48 kHz 20 Hz to 20 kHz 20 Bits 100 pF 47 kΩ 2.4 V 0.
PAGE 3
AD1854 POWER Supplies Voltage, Analog and Digital Analog Current Analog Current—Power-Down Digital Current Digital Current—Power-Down Dissipation Operation—Both Supplies Operation—Analog Supply Operation—Digital Supply Power-Down—Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins Min Typ Max Unit 4.5 26 26 14 1.5 5 30 29 17 2.5 5.5 35 33.5 20 5.
PAGE 4
AD1854 ABSOLUTE MAXIMUM RATINGS* DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering PIN CONFIGURATION Min Max Unit –0.3 –0.3 DGND – 0.3 AGND – 0.3 –0.3 +6 +6 DVDD + 0.3 AVDD + 0.3 +0.3 (AVDD + 0.
PAGE 5
AD1854 PIN FUNCTION DESCRIPTIONS Pin Input/Output Pin Name Description 1 2 I I DGND MCLK 3 4 I I CLATCH CCLK 5 I CDATA 6 I 384/256 7 8 I O X2MCLK ZEROR 9 I DEEMP 10 11, 15 12 13 14 I I O O O 96/48 AGND OUTR+ OUTR– FILTR 16 17 18 19 20 O O I O I OUTL– OUTL+ AVDD FILTB IDPM1 21 I IDPM0 22 O ZEROL 23 I MUTE 24 I PD/RST 25 26 I I L/RCLK BCLK 27 I SDATA 28 I DVDD Digital Ground. Master Clock Input. Connect to an external clock source at either 256, 384 or 512 FS.
PAGE 6
AD1854 Figure 1 shows the right-justified mode (16-bit mode). L/RCLK is HI for the left channel, LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 16-bit clock periods from an L/RCLK transition, so that when there are 64 BCLK periods per L/RCLK period, the LSB of the data will be right justified to the next L/RCLK transition. The right-justified mode can also be used with 20-bit or 24-bit inputs as selected in Table I.
PAGE 7
AD1854 L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 Figure 3. Left-Justified Mode L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL BCLK INPUT SDATA INPUT LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 Figure 4. 32 × FS Packed Mode t CHD t CCP CDATA D15 CCLK D14 D0 t CCH t CCL t CSU t CLL t CLH CLATCH Figure 5.
PAGE 8
AD1854 CLATCH >130ns CCLK CDATA 20 40 60 80 100 120 140 160 180 TIME – ns Figure 6. SPI Port Continuous CCLK Mode CLATCH CCLK CDATA 200 400 600 800 1000 1200 1400 1600 1800 TIME – ns Figure 7. SPI Port Burst Mode Burst Mode Output Drive, Buffering and Loading To operate with SPI CCLK frequencies up to 12.288 MHz, the SPI port can be operated in Burst Mode. This means that when CLATCH is high, CCLK cannot be HI, as shown in Figure 7.
PAGE 9
AD1854 Timing Diagrams minimum setup time is tDDS and the minimum serial data hold time is tDDH. The serial data port timing is shown in Figures 9 and 10. The minimum bit clock HI pulsewidth is tDBH and the minimum bit clock LO pulsewidth is tDBL. The minimum bit clock period is tDBP. The left/right clock minimum setup time is tDLS and the left/right clock minimum hold time is tDLH. The serial data tDBH The power-down/reset timing is shown in Figure 11.
PAGE 10
AD1854 MCLK/SR SELECT SELECT RATE X2MCLK 384/256 96/48 DVDD MCLK/SR SEL JP1 R3 10k R2 10k R1 10k SPDIF DIRECT DIRECT 0 0 1 0 0 0 0 0 0 44.1 48.0 96.0 MCLK 11.2896 12.2880 12.2880 AD1854 STEREO DAC SDATA AUDIO DATA DVDD AVDD C3 100nF C2 100nF OUTPUT BUFFERS AND LP FILTERS LRCLK SCLK DVDD MCLK IDPM1 IDPM0 RJ, 16-BIT I2S RJ, 20-BIT RJ, 24-BIT LJ 0 0 1 1 BCLK C13 1nF, NP0 X2MCLK R17 1.
PAGE 11
AD1854 4 6 8 10 12 14 FREQUENCY – kHz 16 18 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 AMPLITUDE – dBFS –40 –45 –45 –50 –50 –55 –55 –60 –60 –65 –65 –70 –70 –75 –75 –80 –80 –85 –85 dBr – A –40 Figure 16. THD+N vs.
PAGE 12
AD1854 0 –30 –20 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –120 –110 –130 –130 –140 –140 –30 –40 dBr – A –60 –70 –80 –90 –100 0 20 40 60 80 100 FREQUENCY – kHz 120 –150 160 140 –120 0 2 Figure 19. Digital Filter Response 4 6 8 10 12 14 FREQUENCY – kHz 16 18 –150 20 Figure 20. Two-Tone Test OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.