Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LQFP 64

8-Channel DAC with PLL and

Differential Outputs, 192 kHz, 24 Bits

Data Sheet

AD1933

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

PLL generated or direct master clock

Low EMI design

DAC with 110 dB dynamic range and SNR

−96 dB THD + N

3.3 V single supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Differential DAC output

Log volume control with autoramp function

SPI® controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S, and TDM modes

Master and slave modes up to 16-channel input/output

64-lead LQFP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home Theater Systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1933 is a high performance, single chip that provides

eight digital-to-analog converters (DACs) with differential

output using the Analog Devices, Inc., patented multibit sigma-

delta (Σ-Δ) architecture. An SPI port is included, allowing a

microcontroller to adjust volume and many other parameters.

The AD1933 operates from 3.3 V digital and analog supplies.

The AD1933 is available in a 64-lead (differential output) LQFP.

Other members of this family include a single-ended DAC

output version.

The AD1933 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR clock or from an external crystal, the AD1933 eliminates the

need for a separate high frequency master clock and can also be

used with a suppressed bit clock. The DACs are designed using

the latest Analog Devices continuous time architectures to

further minimize EMI. By using 3.3 V supplies, power

consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

AD1933

6.144MHz

ANALOG

AUDIO

OUTPUTS

DIGIT

AL AUDIO

INPUT/OUTPUT

CONTROL DAT

INPUT/OUTPUT

DIGI

TAL

LTER

AND

VOLUME

CONTROL

SERIAL

DATA

PORT

PRECISION

VOLTAGE

REFERENCE

CLOCKS

SDAT

AIN

CONTROL

PORT

SPI

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PULL)

DAC

06624-001

Figure 1.

Summary of content (28 pages)

PAGE 1
8-Channel DAC with PLL and Differential Outputs, 192 kHz, 24 Bits AD1933 Data Sheet FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design DAC with 110 dB dynamic range and SNR −96 dB THD + N 3.
PAGE 2
AD1933 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converters (DACs) .................................... 11 Applications ....................................................................................... 1 Clock Signals ............................................................................... 11 General Description ....................................................................
PAGE 3
Data Sheet AD1933 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) Temperature range 1 Master clock Input sample rate Measurement bandwidth Word width Load capacitance (digital output) Load current (digital output) Input voltage high Input voltage low 1 3.3 V As specified in Table 1 and Table 2 12.
PAGE 4
AD1933 Data Sheet Specifications measured at a case temperature of 125°C. Table 2.
PAGE 5
Data Sheet AD1933 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Test Conditions/Comments Min Typ Max Unit DVDD AVDD VSUPPLY Master clock = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 3.0 3.0 4.5 3.3 3.3 5.0 3.6 3.6 5.
PAGE 6
AD1933 Data Sheet TIMING SPECIFICATIONS −40°C < TC < +125°C, DVDD = 3.3 V ± 10%. Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle DAC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, and 768 fS DAC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode 40 60 % 40 60 % 6.9 13.8 27.
PAGE 7
Data Sheet AD1933 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +6.0 V ±20 mA −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.
PAGE 8
AD1933 Data Sheet NC AVDD LF NC NC NC NC NC NC NC NC CM AVDD NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 AGND MCLKI/XI 2 47 FILTR MCLKO/XO 3 46 AGND AGND 4 45 AVDD AVDD 5 44 AGND OL3P 6 43 OR2N OL3N 7 AD1933 42 OR2P OR3P 8 OL2N OR3N TOP VIEW (Not to Scale) 41 9 40 OL2P OL4P 10 39 OR1N OL4N 11 38 OR1P OR4P 12 37 OL1N OR4N 13 36 OL1P DIFFERENTIAL OUTPUT 23 24 25 26 27 28 29 30 31 32 AUXTDMBCLK A
PAGE 9
Data Sheet AD1933 Pin No. 23 24 25 26 27, 49, 50, 63, 64 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 51 52 Input/Output I I O O Mnemonic VSUPPLY VSENSE VDRIVE AUXDATA1 NC Description 5 V Input to Regulator, Emitter of Pass Transistor. 3.3 V Output of Regulator, Collector of Pass Transistor. Drive for Base of Pass Transistor. AUX DAC1 data out (to external DAC1). No Connect.
PAGE 10
AD1933 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –50 –100 0 8 16 24 FREQUENCY (kHz) 06624-003 –150 –0.06 0 24 48 72 96 FREQUENCY (kHz) 06624-006 –0.04 Figure 6. DAC Stop-Band Filter Response, 96 kHz Figure 3. DAC Pass-Band Filter Response, 48 kHz 0.5 0 0.4 0.2 MAGNITUDE (dB) MAGNITUDE (dB) 0.3 –50 –100 0.1 0 –0.1 –0.2 –0.3 12 24 36 48 FREQUENCY (kHz) –0.5 0 8 32 16 06624-007 0 06624-004 –0.
PAGE 11
Data Sheet AD1933 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1933 DAC channels are arranged as differential, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode).
PAGE 12
AD1933 Data Sheet SERIAL CONTROL PORT The AD1933 has an SPI control port that permits programming and reading back of the internal control registers for the ADCs, DACs, and clock system. A standalone mode is also available for operation without serial control; standalone is configured at reset by connecting CIN, CCLK, and CLATCH to ground. In standalone mode, all registers are set to default, except the internal MCLK enable, which is set to 1.
PAGE 13
Data Sheet AD1933 POWER SUPPLY AND VOLTAGE REFERENCE The AD1933 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PCB as the DAC.
PAGE 14
AD1933 Data Sheet Table 11.
PAGE 15
Data Sheet AD1933 DAISY-CHAIN MODE Again, the first four channels of each TDM input belong to the first AD1933 in the chain and the last four channels belong to the second AD1933. The AD1933 also allows a daisy-chain configuration to expand the system 16 DACs (see Figure 12). In this mode, the DBCLK frequency is 512 fS. The first eight slots of the DAC TDM data stream belong to the first AD1933 in the chain and the last eight slots belong to the second AD1933.
PAGE 16
AD1933 Data Sheet DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 06624-014 32 BITS MSB Figure 14.
PAGE 17
Data Sheet AD1933 tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATA LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATA I2S-JUSTIFIED MODE MSB tDDH tDDS MSB LSB tDDH tDDH 06624-016 tDDS DSDATA RIGHT-JUSTIFIED MODE Figure 16. DAC Serial Timing tABH AUXTDMBCLK tABL tALH tALS AUXTDMLRCLK DSDATA1 I2S-JUSTIFIED MODE MSB MSB–1 MSB DSDATA1 RIGHT-JUSTIFIED MODE MSB Figure 17. AUXTDM Serial Timing Rev.
PAGE 18
AD1933 Data Sheet Table 12.
PAGE 19
Data Sheet AD1933 CONTROL REGISTERS DEFINITIONS The global address for the AD1933 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 13. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 14.
PAGE 20
AD1933 Data Sheet Table 16. PLL and Clock Control 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select Clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 17. DAC Control 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.1 kHz/48 kHz 64 kHz/88.
PAGE 21
Data Sheet AD1933 Table 19. DAC Control 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 20.
PAGE 22
AD1933 Data Sheet AUXILIARY TDM PORT CONTROL REGISTERS Table 22. Auxiliary TDM Control 0 Bit 1:0 4:2 6:5 7 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Reserved Reserved DAC aux mode Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Word width SDATA delay (BCLK periods) Serial format BCLK active edge (TDM in) Table 23.
PAGE 23
Data Sheet AD1933 ADDITIONAL MODES The AD1933 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 19 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1933 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency.
PAGE 24
AD1933 Data Sheet APPLICATION CIRCUITS LRCLK + LF 39nF DAC OUTP MCLK 2.2nF 68pF NPO 3.01kΩ 2 270pF NPO 3 560pF NPO 5.62kΩ 1.50kΩ 390pF 562Ω AVDD2 – 1 OP275 + 604Ω AUDIO OUTPUT 2.2nF NPO 150pF NPO 5.62kΩ 5.6nF 3.32kΩ AVDD2 DAC OUTN 06624-021 LF 11kΩ 11kΩ 06624-022 Typical applications circuits are shown in Figure 21 through Figure 23. Figure 21 shows the recommended loop filters when using either the LR clock or the master clock as the PLL reference.
PAGE 25
Data Sheet AD1933 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 24.
PAGE 26
AD1933 Data Sheet NOTES Rev.
PAGE 27
Data Sheet AD1933 NOTES Rev.