Datasheet
AD1938 Data Sheet
Rev. E | Page 14 of 32
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the
RST
pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After
RST
is deasserted, and the PLL acquires
lock condition, an initialization routine runs inside the AD1938.
This initialization lasts for approximately 256 master clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. To
guarantee proper start up, the
RST
pin should be pulled low by
an external resistor.
SERIAL CONTROL PORT
The AD1938 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal master clock enable which is set to 1,
and ADC BCLK and LRCLK master/slave is set by the COUT
pin. Refer to Table 11 for details. Standalone mode only
supports stereo mode with an I
2
S data format and 256 f
S
master
clock rate. It is recommended to use a weak pull-up resistor on
CLATCH
in applications that have a microcontroller. This pull-
up resistor ensures that the AD1938 recognizes the presence of
a microcontroller.
The SPI control port of the AD1938 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1938, the address is 0x04, shifted left one bit due to the R/
W
bit. The second byte is the AD1938 register address and the
third byte is the data.
Table 11. Standalone Mode Selection
ADC Clocks CIN COUT CCLK
CLATCH
Slave 0 0 0 0
Master 0 1 0 0
D0
D0
D8
D8
D22D23 D9
D9
C
LATCH
CCLK
CIN
COUT
t
CCH
t
CCL
t
CDS
t
CDH
t
CLS
t
CCP
t
CLH
t
COTS
t
COD
t
COE
05582-011
Figure 11. Format of SPI Signal