Datasheet

Data Sheet AD1938
Rev. E | Page 27 of 32
ADC CONTROL REGISTERS
Table 23. ADC Control Register 0
Bit Value Function Description
0
0
Normal
Power-down
1 Power down
1
0
Off
High-pass filter
1 On
2 0 Unmute ADC L1 mute
1 Mute
3 0 Unmute ADC R1 mute
1 Mute
4 0 Unmute ADC L2 mute
1 Mute
5 0 Unmute ADC R2 mute
1 Mute
7:6 00 32 kHz/44.1 kHz/48 kHz Output sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
Table 24. ADC Control Register 1
Bit
Value
Function
Description
1:0 00 24 Word width
01 20
10 Reserved
11 16
4:2
000
1
SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
6:5 00 Stereo Serial format
01 TDM (daisy chain)
10 ADC AUX mode (ADC-, DAC-, TDM-coupled)
11 Reserved
7 0 Latch in mid cycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)