Datasheet

AD1938 Data Sheet
Rev. E | Page 28 of 32
Table 25. ADC Control Register 2
Bit Value Function Description
0 0 50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs) per channel) LRCLK format
1 Pulse (32 BCLKs per channel)
1 0 Drive out on falling edge (DEF) BCLK polarity
1 Drive out on rising edge
2 0 Left low LRCLK polarity
1 Left high
3 0 Slave LRCLK master/slave
1 Master
5:4 00 64 BCLKs per frame
01 128
10 256
11 512
6
0
Slave
BCLK master/slave
1 Master
7 0 ABCLK pin BCLK source
1 Internally generated