Datasheet

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4 ADC/8 DAC with PLL,

192 kHz, 24-Bit Codec

Data Sheet

AD1939

Rev. E Document Feedback

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FEATURES

PLL generated or direct master clock

Low EMI design

112 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24-bits and 8 kHz to 192 kHz sample rates

Differential ADC input

Differential DAC output

Log volume control with autoramp function

SPI controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I

S, and TDM modes

Master and slave modes up to 16-channel input/output

64-lead LQFP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home Theater Systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1939 is a high performance, single-chip codec that

provides four analog-to-digital converters (ADCs) with

differential input, and eight digital-to-analog converters (DACs)

with differential output using the Analog Devices, Inc. patented

multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,

allowing a microcontroller to adjust volume and many other

parameters. The AD1939 operates from 3.3 V digital and analog

supplies. The AD1939 is available in a 64-lead (differential

output) LQFP package.

The AD1939 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR clock or from an external crystal, the AD1939 eliminates

the need for a separate high frequency master clock and can

also be used with a suppressed bit clock. The DACs and ADCs

are designed using the latest Analog Devices continuous time

architectures to further minimize EMI. By using 3.3 V supplies,

power consumption is minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

DIGITAL

FILTER

SERIAL DATA PORT

DIGITAL AUDIO

INPUT/OUTPUT

PRECISION

VOLTAGE

REFERENCE

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

SPI

CONTROL PORT

CONTROL DATA

INPUT/OUTPUT

AD1939

ADC

ANALOG

AUDIO

INPUTS

ANALOG

AUDIO

OUTPUTS

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

SDATA

OUT

SDATA

CLOCKS

06071-001

Figure 1.

Summary of content (32 pages)

PAGE 1
4 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec AD1939 Data Sheet FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N Single 3.
PAGE 2
AD1939 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs) .................................... 13 Applications ....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 13 General Description .........................................................................
PAGE 3
Data Sheet AD1939 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) Temperature range1 Master clock Input sample rate Measurement bandwidth Word width Load capacitance (digital output) Load current (digital output) Input voltage high Input voltage low 1 3.3 V As specified in Table 1 and Table 2 12.
PAGE 4
AD1939 Parameter Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output REGULATOR Input Supply Voltage Regulated Output Voltage Data Sheet Conditions/Comments Min Typ 0 0.375 95 Max ±0.6 100 Unit Degrees dB dB dB Ω FILTR pin FILTR pin CM pin 1.32 1.50 1.50 1.50 1.68 V V V VSUPPLY pin VSENSE pin 4.5 3.19 5 3.37 5.5 3.
PAGE 5
Data Sheet AD1939 DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +105°C, DVDD = 3.3 V ± 10%. Table 4. Parameter High Level Input Voltage (VIH) Conditions/Comments MCLKI/XI pin Low Level Input Voltage (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V IOH = 1 mA IOL = 1 mA Min 2.0 2.2 Typ Max 0.4 5 Unit V V V µA µA V V pF 0.8 10 10 DVDD − 0.60 POWER SUPPLY SPECIFICATIONS Table 5.
PAGE 6
AD1939 Data Sheet DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typical @ 48 kHz Factor Min 0.4375 fS Typ Max Unit 21 ±0.015 24 27 0.5 fS 0.5625 fS kHz dB kHz kHz dB µs 79 22.
PAGE 7
Data Sheet Parameter SPI PORT tCCH tCCL fCCLK tCDS tCDH tCLS tCLH tCLHIGH tCOE tCOD tCOH tCOTS DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLS tDDS tDDH ADC SERIAL PORT tABH tABL tALS tALH tALS tABDD AUXILIARY INTERFACE tAXDS tAXDH tDXDD tXBH tXBL tDLS tDLH AD1939 Condition CCLK high CCLK low CCLK frequency CIN setup CIN hold CLATCH setup CLATCH hold CLATCH high COUT enable COUT delay COUT hold COUT tristate DBCLK high DBCLK low DLRCLK setup DLRCLK hold DLRCLK skew DSDATA setup DSDATA hold ABCLK high ABCLK low AL
PAGE 8
AD1939 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +6.0 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.
PAGE 9
Data Sheet AD1939 51 50 49 AGND 1 48 AGND MCLKI/XI 2 47 FILTR MCLKO/XO 3 46 AGND AGND 4 45 AVDD AVDD 5 44 AGND OL3P 6 43 OR2N OL3N 7 AD1939 42 OR2P OR3P 8 OL2N OR3N TOP VIEW (Not to Scale) 41 9 40 OL2P DIFFERENTIAL OUTPUT OL4P 10 39 OR1N OL4N 11 38 OR1P NC = NO CONNECT 22 23 24 25 26 27 28 29 30 31 32 DVDD 21 CIN 20 COUT 19 ABCLK 18 ALRCLK DVDD 17 ASDATA1 DGND VDRIVE 33 ASDATA2 CCLK DGND 16 VSENSE 34 VSUPPLY CLATCH DSDATA4 1
PAGE 10
AD1939 Data Sheet Pin No.
PAGE 11
Data Sheet AD1939 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0 0.08 0.06 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –0.04 –50 –100 –0.06 –150 0 2 4 6 8 10 12 14 16 06071-002 –0.10 18 FREQUENCY (kHz) 0 12 24 36 48 FREQUENCY (kHz) Figure 3. ADC Pass-Band Filter Response, 48 kHz 06071-005 –0.08 Figure 6. DAC Stop-Band Filter Response, 48 kHz 0 0.10 –10 –20 0.05 MAGNITUDE (dB) MAGNITUDE (dB) –30 –40 –50 –60 –70 0 –0.05 –80 5 10 15 20 25 30 35 –0.
PAGE 12
AD1939 Data Sheet 0.5 0 0.4 0.3 –2 MAGNITUDE (dB) 0.1 0 –0.1 –4 –6 –0.2 –8 –0.3 –0.5 0 8 16 32 64 FREQUENCY (kHz) –10 48 64 80 FREQUENCY (kHz) Figure 10. DAC Stop-Band Filter Response, 192 kHz Figure 9. DAC Pass-Band Filter Response, 192 kHz Rev. E | Page 12 of 32 96 06071-009 –0.4 06071-008 MAGNITUDE (dB) 0.
PAGE 13
Data Sheet AD1939 THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four analog-to-digital converter (ADC) channels in the AD1939 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs include on-board digital antialiasing filters with 79 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz modes).
PAGE 14
AD1939 Data Sheet master clock. In addition, it is especially important that the clock signal not pass through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1939. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter.
PAGE 15
Data Sheet AD1939 POWER SUPPLY AND VOLTAGE REFERENCE The AD1939 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. To minimize noise pickup, these pins should be bypassed with 100 nF ceramic chip capacitors placed as close to the pins as possible. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PC board as the codec.
PAGE 16
AD1939 Data Sheet Combining the AUX ADC and DAC modes results in a system configuration of 8 ADCs and 12 DACs. The system, then, consists of two external stereo ADCs, two external stereo DACs, and one AD1939. This mode is shown in Figure 17 (combined AUX DAC and ADC modes). Table 12.
PAGE 17
Data Sheet AD1939 ALRCLK ABCLK 8 ON-CHIP DAC CHANNELS DSDATA1 (TDM_IN) DAC L1 ASDATA1 (TDM_OUT) ADC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 ADC R2 AUX L1 AUX R1 4 ON-CHIP ADC CHANNELS ADC R1 DAC L4 DAC R4 4 AUX ADC CHANNELS ADC L2 AUX L2 AUX R2 32 BITS MSB DLRCLK (AUX PORT) LEFT RIGHT DSDATA2 (AUX1_IN) MSB MSB DSDATA3 (AUX2_IN) MSB MSB 06071-050 DBCLK (AUX PORT) Figure 15.
PAGE 18
AD1939 Data Sheet ALRCLK ABCLK UNUSED SLOTS DSDATA1 (TDM_IN) EMPTY ASDATA1 (TDM_OUT) ADC L1 DLRCLK (AUX PORT) EMPTY EMPTY EMPTY 4 ON-CHIP ADC CHANNELS ADC R1 ADC L2 AUXILIARY DAC CHANNELS APPEAR AT AUX DAC PORTS 8 ON-CHIP DAC CHANNELS ADC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 AUXILIARY ADC CHANNELS AUX L1 AUX R1 AUX L2 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED SLOTS AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED LEFT RIGHT DSDATA2 (AUX1_IN)
PAGE 19
Data Sheet AD1939 There are two configurations for the ADC port to work in daisy-chain mode. The first one is with an ABCLK at 256 fS shown in Figure 21. The second configuration is shown in Figure 22. Note that in the 512 fS ABCLK mode, the ADC channels occupy the first eight slots; the second eight slots are empty. The TDM_IN of the first AD1939 must be grounded in all modes of operation.
PAGE 20
AD1939 Data Sheet DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (IN) DAC L1 DAC R1 DAC L2 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC R2 DSDATA2 (OUT) DSDATA3 (IN) DAC L3 DAC R3 DAC L4 DAC R4 DSDATA4 (OUT) DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS FIRST AD1939 SECOND AD1939 06071-055 MSB DSP Figure 19.
PAGE 21
Data Sheet AD1939 ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN 4 ADC CHANNELS OF FIRST IC IN THE CHAIN ASDATA1 (TDM_OUT OF THE SECOND AD1939 IN THE CHAIN) ADC L1 ADC R1 ADC L2 ADC R2 ASDATA2 (TDM_IN OF THE SECOND AD1939 IN THE CHAIN) ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2 32 BITS SECOND AD1939 DSP 06071-057 FIRST AD1939 MSB Figure 22.
PAGE 22
AD1939 Data Sheet tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATAx LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATAx I2S-JUSTIFIED MODE MSB tDDH tDDS MSB LSB tDDH tDDH 06071-014 tDDS DSDATAx RIGHT-JUSTIFIED MODE Figure 24. DAC Serial Timing tABH ABCLK tABL tALH tALS ALRCLK tABDD ASDATAx LEFT-JUSTIFIED MODE MSB MSB–1 tABDD ASDATAx I2S-JUSTIFIED MODE MSB ASDATAx RIGHT-JUSTIFIED MODE MSB Figure 25. ADC Serial Timing Rev.
PAGE 23
Data Sheet AD1939 Table 13.
PAGE 24
AD1939 Data Sheet CONTROL REGISTERS DEFINITIONS The global address for the AD1939 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 15.
PAGE 25
Data Sheet AD1939 Table 17. PLL and Clock Control 1 Register Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select ADC clock source select On-chip voltage reference PLL lock indicator (read only) DAC CONTROL REGISTERS Table 18. DAC Control 0 Register Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.
PAGE 26
AD1939 Data Sheet Table 20. DAC Control 2 Register Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 21.
PAGE 27
Data Sheet AD1939 ADC CONTROL REGISTERS Table 23. ADC Control 0 Register Bit 0 1 2 3 4 5 7:6 Value 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 Function Normal Power down Off On Unmute Mute Unmute Mute Unmute Mute Unmute Mute 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved Description Power-down High-pass filter ADC 1L mute ADC 1R mute ADC 2L mute ADC 2R mute Output sample rate Table 24.
PAGE 28
AD1939 Data Sheet Table 25. ADC Control 2 Register Bit 0 1 2 3 5:4 6 7 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs) per channel) Pulse (32 BCLKs per channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 128 256 512 Slave Master ABCLK pin Internally generated Rev.
PAGE 29
Data Sheet AD1939 ADDITIONAL MODES The AD1939 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1939 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency.
PAGE 30
AD1939 Data Sheet APPLICATION CIRCUITS Typical application circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in Figure 31 and a regulator circuit is shown in Figure 32. 120pF 5.76kΩ 5.76kΩ 100pF 3 11kΩ – 1 OP275 DAC OUTN + 4.7µF 237Ω 5.76kΩ + 120pF 6 5 OP275 ADCxN DAC OUTP 1nF NPO 1nF NPO 4.
PAGE 31
Data Sheet AD1939 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 33.