Datasheet

AD1939 Data Sheet
Rev. E | Page 30 of 32
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended
loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in
Figure 31 and a regulator circuit is shown in Figure 32.
2
1
3
OP275
–
+
6
7
5
OP275
–
+
5.76kΩ
5.76kΩ 237Ω
5.76kΩ
120pF
600Z
AUDIO
INPUT
100pF
5.76kΩ
120pF
4.7µF
+
237Ω
4.7µF
+
100pF
1nF
NPO
1nF
NPO
ADCxN
ADCxP
06071-029
Figure 29. Typical ADC Input Filter Circuit
39nF
+
2.2nF
LF
LRCLK
AVDD2
3.32kΩ
5.6nF
390pF
LF
MCLK
AVDD2
562Ω
06071-030
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
06071-031
2
1
3
OP275
–
+
2.2nF
NPO
AUDIO
OUTPUT
604Ω
68pF
NPO
560pF
NPO
270pF
NPO
DAC
OUTN
3.01kΩ11kΩ
DAC
OUTP
1.50kΩ5.62kΩ
11kΩ
5.62kΩ
Figure 31. Typical DAC Output Filter Circuit (Differential)
10µF
+
E
C
B
VSUPPLY 5V
VSENSE
3.3V
FZT953
VDRIVE
1kΩ
100nF
10µF
+
100nF
06071-032
Figure 32. Recommended 3.3 V Regulator Circuit