Datasheet

AD1974 Data Sheet
Rev. D | Page 18 of 24
CONTROL REGISTERS
The global address for the AD1974 is 0x04, shifted left one bit due to the R/
W
bit. All registers are reset to 0.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address R/
W
Register Address Data
Bit
23:17 16 15:8 7:0
Table 15. Register Addresses Description
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 AUXPORT Control 0
3 AUXPORT Control 1
4 AUXPORT Control 2
5 Reserved
6 Reserved
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 ADC Control 0
15
ADC Control 1
16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01
INPUT 384 (×44.1 kHz or 48 kHz)
10 INPUT 512 (×44.1 kHz or 48 kHz)
11 INPUT 768 (×44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5 00 MCLKI/XI PLL input
01 AUXLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC idle Internal MCLK enable
1 Enable: ADC active