Datasheet

Data Sheet AD1974
Rev. D | Page 23 of 24
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a typical ADC input filter circuit. Recommended loop
filters for LR clock and master clock as the PLL reference are shown in Figure 18.
2
1
3
OP275
–
+
6
7
5
OP275
–
+
5.76kΩ
5.76kΩ 237Ω
5.76kΩ
120p
F
600Z
A
UDIO
INPUT
100pF
5.76kΩ
120pF
4.7µF
+
237Ω
4.7µF
+
100pF
1nF
NP0
1nF
NP0
ADCxN
ADCxP
06614-023
Figure 17. Typical ADC Input Filter Circuit
39nF
+
2.2nF
LF
LRCL
K
A
VDD2
3.32kΩ
5.6nF
390pF
LF
MCLK
AVDD2
562Ω
06614-027
Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference