Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - ADC 12 Bit LQFP 44

12-Bit R/D Converter

with Reference Oscillator

AD2S1200

Rev. 0

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FEATURES

Complete monolithic R/D converter

Parallel and serial 12-bit data ports

System fault detection

Absolute position and velocity outputs

Differential inputs

±11 arc minutes of accuracy

1,000 rps maximum tracking rate, 12-bit resolution

Incremental encoder emulation (1,024 pulses/rev)

Programmable sinusoidal oscillator on-board

Compatible with DSP and SPI® interface standards

204.8 kHz square wave output

Single-supply operation (5.00 V ± 5%)

−40°C to +125°C temperature rating

44-lead LQFP package

4 kV ESD protection

GENERAL DESCRIPTION

The AD2S1200 is a complete 12-bit resolution tracking resolver-

to-digital converter, integrating an on-board programmable

sinusoidal oscillator that provides sine wave excitation for

resolvers. An external 8.192 MHz crystal is required to provide

a precision time reference. This clock is internally divided to

generate a 4.096 MHz clock to drive all the peripherals.

The converter accepts 3.6 V p-p ± 10% input signals, in the

range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II

servo loop is employed to track the inputs and convert the input

Sin and Cos information into a digital representation of the

input angle and velocity. The bandwidth of the converter is set

internally to 1.7 kHz with an external 8.192 MHz crystal. The

maximum tracking rate is 1,000 rps.

FUNCTIONAL BLOCK DIAGRAM

04406-0-001

REFERENCE

OSCILLATOR

(DAC)

ADC

SinLO

Sin

ANGLE θ

ANGLE φ

ADC

CosLO

Cos

EXC

SAMPLE

MONITOR

ERROR

MONITOR

(204.8kHz)

CPO

REFBYP REFOUT FS1 FS2 XTALOUT

CLKIN

(8.192MHz)

DOS

LOT

DIR

(4.096MHz)

ERROR

CALCULATION/

SIGNAL

MONITOR

DEMODULATOR

POSITION

INTEGRATOR

POSITION REGISTER

MULTIPLEXER

DB11

SOERDVELRESET DB10

SCLK

DB9–DB0

AD2S1200

DATA BUS OUTPUT

VELOCITY REGISTER

ENCODER

EMULATION

SYNTHETIC

REFERENCE

VOLTAGE

REFERENCE

INTERNAL

CLOCK

GENERATOR

CLOCK

DIVIDER

FAULT

INDICATORS

DIGITAL

FILTER

VELOCITY

INTEGRATOR

Figure 1.

Summary of content (24 pages)

PAGE 1
2-Bit R/D Converter with Reference Oscillator AD2S1200 FEATURES GENERAL DESCRIPTION Complete monolithic R/D converter Parallel and serial 12-bit data ports System fault detection Absolute position and velocity outputs Differential inputs ±11 arc minutes of accuracy 1,000 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1,024 pulses/rev) Programmable sinusoidal oscillator on-board Compatible with DSP and SPI® interface standards 204.
PAGE 2
AD2S1200 APPLICATIONS Electric power steering Electric vehicles Integrated starter generator/alternator Encoder emulation Automotive motion sensing and control • Triple Format Position Data: Absolute 12-bit angular binary position data accessed either via a 12-bit parallel port or via a 3-wire serial interface. Incremental encoder emulation in standard A QUAD B format, with direction output is available.
PAGE 3
AD2S1200 TABLE OF CONTENTS AD2S1200–Specifications ................................................................4 Incremental Encoder Outputs...................................................16 Absolute Maximum Ratings ............................................................6 On-Board Programmable Sinusoidal Oscillator.....................16 ESD Caution ..................................................................................6 Supply Sequencing and Reset................................
PAGE 4
AD2S1200 AD2S1200–SPECIFICATIONS Table 1. (AVDD = DVDD = 5.0 V ± 5% @ −40°C to +125°C CLKIN 8.192 MHz, unless otherwise noted.) Parameter Sin, Cos INPUTS1 Voltage Input Bias Current Input Impedance Common Mode Volts Phase Lock Range ANGULAR ACCURACY Angular Accuracy Min Typ Max Unit Conditions/Comments 3.24 3.6 3.96 2 V p-p µA MΩ mV Peak Degrees Sinusoidal waveforms, differential inputs VIN = 3.96 V p-p VIN = 3.96 V p-p CMV @ SinLO, CosLO, with respect to REFOUT @ 10 kHz Sin/Cos vs.
PAGE 5
AD2S1200 Parameter FAULT DETECTION BLOCK (CONT.) DOS Sin/Cos Threshold Sin/Cos Mismatch Min Typ Max Unit Conditions/Comments 4.0 4.09 385 4.2 420 V p-p mV 30 Degrees 60 125 Degrees µs DOS goes low when Sin or Cos exceeds threshold. DOS latched low when Sin/Cos amplitude mismatch exceeds the threshold. DOS indicated before angular output error exceeds limit. Maximum electrical rotation before DOS is indicated.
PAGE 6
AD2S1200 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VDD) Supply Voltage (AVDD) Input Voltage Output Voltage Swing Operating Temperature Range (Ambient) Storage Temperature Range Lead Temperature Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7.0 V −0.3 V to + 7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 7
AD2S1200 EXC EXC AGND Sin SinLO AVDD CosLO Cos AGND REFBYP REFOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 DVDD 1 33 RESET RD 2 32 FS2 CS 3 31 FS1 SAMPLE 4 30 LOT RDVEL 5 AD2S1200 29 DOS SOE 6 TOP VIEW (Not to Scale) 28 DIR 27 NM DB10/SCLK 8 26 B DB9 9 25 A DB8 10 24 CPO DB7 11 23 DGND 04406-0-002 DB11/SO 7 CLKIN DB0 XTALOUT DB1 DB2 DVDD DGND DB3 DB4 DB5 DB6 12 13 14 15 16 17 18 19 20 21 22 Figure 2.
PAGE 8
AD2S1200 RESOLVER FORMAT SIGNALS Vr = Vp × Sin(ϖt) Vr = Vp × Sin(ϖt) R1 S2 S2 Va = Vs × Sin(ϖt) × Cos(θ) θ R1 Va = Vs × Sin(ϖt) × Cos(θ) θ S4 S4 R2 R2 S3 S1 S3 Vb = Vs × Sin(ϖt) × Sin(θ) Vb = Vs × Sin(ϖt) × Sin(θ) (A) CLASSICAL RESOLVER (B) VARIABLE RELUCTANCE RESOLVER 04406-0-003 S1 Figure 3. Classical Resolver vs. Variable Reluctance Resolver A resolver is a rotating transformer typically with a primary winding on the rotor and two secondary windings on the stator.
PAGE 9
AD2S1200 PRINCIPLE OF OPERATION The AD2S1200 operates on a Type II tracking closed-loop principle. The output continually tracks the position of the resolver without the need for external convert and wait states. As the resolver moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB.
PAGE 10
AD2S1200 Signal Degradation Detection Responding to a Fault Condition Degradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold by comparing the monitor signal to a fixed maximum value. DOS is also detected when the amplitude of the input signals If any fault condition (LOS, DOS, or LOT) is indicated by the AD2S1200, the output data must be presumed to be invalid.
PAGE 11
AD2S1200 CONNECTING THE CONVERTER Refer to Figure 5. Ground should be connected to the AGND pin and DGND pin. Positive power supply VDD = +5 V dc ± 5% should be connected to the AVDD pin and DVDD pin. Typical values for the decoupling capacitors are 10 nF and 4.7 µF, respectively. These capacitors should be placed as close to the device pins as possible, and should be connected to both AVDD and DVDD.
PAGE 12
AD2S1200 ABSOLUTE POSITION AND VELOCITY OUTPUT The angular position and angular velocity are represented by binary data and can be extracted either via a 12-bit parallel interface or a 3-wire serial interface that operates at clock rates up to 25 MHz. The chip select pin, CS, must be held low to enable the device. Angular position and velocity can be selected using a dedicated polarity input, RDVEL. SOE Input The serial output enable pin, SOE, is held high to enable the parallel interface.
PAGE 13
AD2S1200 tCK CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 DON'T CARE t6 VEL t7 04406-0-007 POS DATA t7 t6 Figure 7. Parallel Port Read Timing Table 5. Parallel Port Timing Parameter tCK t1 t2 t3 t4 t5 t6 t7 Description Clock Period (= 1/8.192 MHz) SAMPLE Pulse Width Delay from SAMPLE before RD/CS Low RD Pulse Width Set Time RDVEL before RD/CS Low Hold Time RDVEL after RD/CS Low Enable Delay RD/CS Low to Data Valid Disable Delay RD/CS Low to Data High Z Rev.
PAGE 14
AD2S1200 SERIAL INTERFACE SAMPLE Input The angular position and angular velocity are available on the AD2S1200 in two 12-bit registers. These registers can be accessed via a 3-wire serial interface, SO, RD, and SCLK, that operates at clock rates up to 25 MHz and is compatible with SPI and DSP interface standards. The serial interface is selected by holding low the SOE pin. Data from the position and velocity integrators are first transferred to the position and velocity registers, using the SAMPLE pin.
PAGE 15
AD2S1200 tCK CLKIN t1 t1 SAMPLE t2 CS t3 t3 RD t5 t5 RDVEL t4 t4 t6 t6 t7 t7 POS SO VEL t8 RD tSCLK SCLK t10 MSB MSB–1 LSB RDVEL DOS LOT PAR 04406-0-008 SO t11 t9 Figure 8. Serial Port Read Timing Table 6. Serial Port Timing Parameter t8 t9 t10 t11 tSCLK Description MSB Read Time from RD/CS to SCLK Enable Time RD/CS to DB Valid Delay SCLK to DB Valid Disable Time RD/CS to DB High Z Serial Clock Period (25 MHz Max) Rev.
PAGE 16
AD2S1200 INCREMENTAL ENCODER OUTPUTS The incremental encoder emulation outputs A, B, and NM are free running and are always valid, providing that valid resolver format input signals are applied to the converter. The AD2S1200 emulates a 1024-line encoder. Relating this to converter resolution means one revolution produces 1,024 A, B pulses. A leads B for increasing angular rotation (i.e., clockwise direction). The addition of the DIR output negates the need for external A and B direction decode logic.
PAGE 17
AD2S1200 Synthetic Reference Generation When a resolver undergoes a high rotation rate, the RDC tends to act as an electric motor and produces speed voltages, along with the ideal Sin and Cos outputs. These speed voltages are in quadrature to the main signal waveform. Moreover, nonzero resistance in the resolver windings causes a non-zero phase shift between the reference input and the Sin and Cos outputs.
PAGE 18
AD2S1200 CIRCUIT DYNAMICS AD2S1200 LOOP RESPONSE MODEL θIN k1 × k2 – The closed-loop magnitude and phase responses are that of a second-order low-pass filter (see Figure 12 and Figure 13). VELOCITY c 1–z –1 1–az –1 1–bz –1 c 1–z –1 θOUT 04406-0-011 ERROR (ACCELERATION) Sin/Cos LOOKUP To convert G(z) into the s-plane, we perform an inverse bilinear transformation by substituting for z, where T = the sampling period (1/4.096 MHz ≈ 244 ns). 2 +s T z= 2 −s T Figure 11.
PAGE 19
AD2S1200 5 SOURCES OF ERROR –0 Acceleration –5 A tracking converter employing a Type II servo loop does not suffer any velocity lag. There is, however, an error associated with acceleration. This error can be quantified using the acceleration constant (Ka) of the converter. MAGNITUDE (dB) –10 –15 –20 –25 Ka = –30 04406-0-012 –35 –40 –45 1 10 100 1k 10k Input Acceleration Tracking Error Conversely, Tracking Error = 100k Input Acceleration Ka FREQUENCY (Hz) Figure 12.
PAGE 20
AD2S1200 CLOCK REQUIREMENTS To achieve the specified dynamic performance, an external crystal of 8.192 MHz must be used at the CLKIN, XTALOUT pins. The position and velocity accuracy are guaranteed for operation with a 8.192 MHz clock. However, the position accuracy will still be maintained for clock frequencies ±10% around this value.
PAGE 21
AD2S1200 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 12.00 BSC 44 34 1 33 SEATING PLANE PIN 1 10.00 BSC TOP VIEW (PINS DOWN) 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE VIEW A 11 23 12 0.80 BSC VIEW A 22 0.45 0.37 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BCB Figure 17.
PAGE 22
AD2S1200 NOTES Rev.
PAGE 23
AD2S1200 NOTES Rev.