Datasheet

AD2S1205
Rev. A | Page 13 of 20
RD
Input
CS
Input
The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when
CS
and
RD
are held
low. A falling edge of the
RD
signal transfers data to the output
buffer. The selected data is made available to the bus to be read
within t
6
of the
RD
pin going low. The data pins return to a high
impedance state when the
RD
pin returns to a high state within
t
7
. When reading data continuously, wait a minimum of t
3
after
RD
is released before reapplying it.
The device is enabled when
CS
is held low.
RDVEL
Input
RDVEL
input is used to select between the angular position
register and the angular velocity register, as shown in . Figure 7
RDVEL
is held high to select the angular position register and
low to select the angular velocity register. The
RDVEL
pin must
be set (stable) at least t
4
before the
RD
pin is pulled low.
06339-007
t
3
t
6
t
7
f
CLKIN
CLKIN
DATA
DON'T CARE
VELOCITYPOSITION
t
2
SAMPLE
CS
RD
RDVEL
t
1
t
1
t
3
t
5
t
4
t
5
t
4
t
7
t
6
Figure 7. Parallel Port Read Timing
Table 6. Parallel Port Timing
Parameter Description Min Typ Max Unit
f
CLKIN
Frequency of clock input 6.144 8.192 10.24 MHz
t
1
SAMPLE
pulse width
2 × (1/f
CLKIN
) + 20 ns
t
2
Delay from SAMPLE
before RD/CS low
6 × (1/f
CLKIN
) + 20 ns
t
3
RD
pulse width
18 ns
t
4
Set time RDVEL
before RD/CS low
5 ns
t
5
Hold time RDVEL
after RD/CS low
7 ns
t
6
Enable delay RD
/CS low to data valid
30 ns
t
7
Disable delay RD
/CS low to data high-Z
18 ns