Datasheet

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Quad Channel, 128-/256-Position, I

Nonvolatile Digital Potentiometer

Data Sheet

AD5123/AD5143

Rev. A Document Feedback

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FEATURES

10 kΩ and 100 kΩ resistance options

Resistor tolerance: 8% maximum

Wiper current: ±6 mA

Low temperature coefficient: 35 ppm/°C

Wide bandwidth: 3 MHz

Fast start-up time < 75 μs

Linear gain setting mode

Single- and dual-supply operation

Wide operating temperature: −40°C to +125°C

3 mm × 3 mm package

4 kV ESD protection

APPLICATIONS

Portable electronics level adjustment

LCD panel brightness and contrast controls

Programmable filters, delays, and time constants

Programmable power supplies

FUNCTIONAL BLOCK DIAGRAM

GND

7/8

SERIAL

INTERFACE

POWER-ON

RESET

RDAC1

INPUT

RDAC2

INPUT

RDAC3

INPUT

RDAC4

INPUT

EEPROM

MEMORY

AD5123/AD5143

SCL

SDA

DDR

10878-001

Figure 1.

GENERAL DESCRIPTION

The AD5123/AD5143 potentiometers provide a nonvolatile

solution for 128-/256-position adjustment applications, offering

guaranteed low resistor tolerance errors of ±8% and up to ±6 mA

current density in the Ax, Bx, and Wx pins.

The low resistor tolerance and low nominal temperature coefficient

simplify open-loop applications as well as applications requiring

tolerance matching.

The linear gain setting mode allows independent programming

of the resistance between the digital potentiometer terminals,

through the R

and R

string resistors, allowing very accurate

resistor matching.

The high bandwidth and low total harmonic distortion (THD)

ensure optimal performance for ac signals, making the devices

suitable for filter design.

The low wiper resistance of only 40 Ω at the ends of the resistor

array allows for pin-to-pin connection.

The wiper values can be set through an I

C-compatible digital

interface that is also used to read back the wiper register and

EEPROM contents.

The AD5123/AD5143 are available in a compact, 16-lead, 3 mm ×

3 mm LFCSP. The parts are guaranteed to operate over the extended

industrial temperature range of −40°C to +125°C.

Table 1. Family Models

Model Channel Position Interface Package

AD5123

Quad 128 I

C LFCSP

AD5124 Quad 128 SPI/I

C LFCSP

AD5124 Quad 128 SPI TSSOP

AD5143 Quad 256 I

C LFCSP

AD5144 Quad 256 SPI/I

C LFCSP

AD5144 Quad 256 SPI TSSOP

AD5144A Quad 256 I

C TSSOP

AD5122 Dual 128 SPI LFCSP/TSSOP

AD5122A Dual 128 I

C LFCSP/TSSOP

AD5142 Dual 256 SPI LFCSP/TSSOP

AD5142A Dual 256 I

C LFCSP/TSSOP

AD5121 Single 128 SPI/I

C LFCSP

AD5141 Single 256 SPI/I

C LFCSP

Two potentiometers and two rheostats.

Summary of content (28 pages)

PAGE 1
Quad Channel, 128-/256-Position, I2C, Nonvolatile Digital Potentiometer AD5123/AD5143 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 μs Linear gain setting mode Single- and dual-supply operation Wide operating temperature: −40°C to +125°C 3 mm × 3 mm package 4 kV ESD protection AD5123/AD5143 POWER-ON RESET RDAC1 A1 INPUT REGIST
PAGE 2
AD5123/AD5143 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 RDAC Register and EEPROM .................................................. 19 Functional Block Diagram ........................................................
PAGE 3
Data Sheet AD5123/AD5143 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5123 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 2.
PAGE 4
AD5123/AD5143 Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current EEPROM Store Current3
PAGE 5
Data Sheet Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time AD5123/AD5143 Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.
PAGE 6
AD5123/AD5143 Data Sheet ELECTRICAL CHARACTERISTICS—AD5143 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 3.
PAGE 7
Data Sheet Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current EEPROM Store Current3, 6
PAGE 8
AD5123/AD5143 Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Data Sheet Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.
PAGE 9
Data Sheet AD5123/AD5143 INTERFACE TIMING SPECIFICATIONS VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 10
AD5123/AD5143 Data Sheet SHIFT REGISTER AND TIMING DIAGRAMS C3 C2 C1 C0 A3 A2 A1 DB8 DB7 A0 D7 DB0 (LSB) D6 D5 D4 D3 D2 D1 D0 10878-002 DB15 (MSB) DATA BITS ADDRESS BITS CONTROL BITS Figure 2. Input Shift Register Contents t11 t12 t6 t8 t2 SCL t5 t1 t6 t4 t10 t3 t9 t7 P S S 2 Figure 3. I C Serial Interface Timing Diagram (Typical Write Sequence) Rev.
PAGE 11
Data Sheet AD5123/AD5143 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VSS to GND VDD to VSS VA, VW, VB to GND Rating −0.3 V to +7.0 V +0.3 V to −7.0 V 7V VSS − 0.3 V, VDD + 0.3 V or +7.
PAGE 12
AD5123/AD5143 Data Sheet PIN 1 INDICATOR A1 1 B3 5 A2 7 TOP VIEW (Not to Scale) 12 VDD 11 B4 10 W4 9 B2 W2 8 W3 4 VSS 6 B1 3 AD5123/ AD5143 W1 2 NOTES 1. INTERNALLY CONNECT THE EXPOSED PAD TO VSS. 10878-004 14 SDA 13 SCL 16 GND 15 ADDR PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No.
PAGE 13
Data Sheet AD5123/AD5143 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 0.4 0.3 0.1 0 R-DNL (LSB) R-INL (LSB) 0.2 0.1 0 –0.1 –0.1 –0.2 –0.3 –0.2 –0.4 –0.3 100 0 200 CODE (Decimal) –0.6 10878-005 –0.5 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 100 0 200 CODE (Decimal) Figure 5. R-INL vs. Code (AD5143) 10878-008 –0.5 –0.4 Figure 8. R-DNL vs. Code (AD5143) 0.20 0.10 0.
PAGE 14
AD5123/AD5143 Data Sheet 0.15 0.06 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.10 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.02 0 0.05 –0.02 DNL (LSB) INL (LSB) 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0.04 0 –0.04 –0.06 –0.05 –0.08 –0.10 –0.10 –0.
PAGE 15
Data Sheet AD5123/AD5143 10 0 0x80 (0x40) 0 –10 0x40 (0x20) 0x20 (0x10) 0x20 (0x10) –20 0x10 (0x08) 0x8 (0x04) GAIN (dB) GAIN (dB) –20 0x10 (0x08) 0x8 (0x04) –30 0x80 (0x40) –10 0x40 (0x20) 0x4 (0x02) 0x2 (0x01) –40 0x1 (0x00) –30 0x4 (0x02) –40 –50 0x2 (0x01) 0x1 (0x00) 0x00 –60 0x00 –70 –50 –80 1k 10k 100k 1M 10M FREQUENCY (Hz) –90 10 10878-017 100 100 –50 0 1M 10M 10kΩ 100kΩ –10 –20 –60 –30 THD + N (dB) THD + N (dB) 100k Figure 20. 100 kΩ Gain vs.
PAGE 16
AD5123/AD5143 Data Sheet 300 200 0.8 0.0015 0.6 0.0010 0.4 0.0005 0.
PAGE 17
Data Sheet 0 AD5123/AD5143 7 10kΩ 100kΩ SHUTDOWN MODE ENABLED 6 THEORETICAL IMAX (mA) –20 –60 –80 5 4 3 2 10kΩ –100 1 100kΩ 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 0 0 50 25 100 150 50 75 CODE (Decimal) 200 100 250 AD5143 125 AD5123 Figure 30. Theoretical Maximum Current vs. Code Figure 29. Shutdown Isolation vs. Frequency Rev.
PAGE 18
AD5123/AD5143 Data Sheet TEST CIRCUITS Figure 31 to Figure 35 define the test conditions used in the Specifications section. NC VA IW V+ = VDD ±10% VDD B V+ VMS ~ Figure 31. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSRR (dB) = 20 LOG W B 10878-031 NC = NO CONNECT A VMS PSS (%/%) = RSW = ΔVDD% 0.1V ISW CODE = 0x00 W V+ B VMS B A = NC Figure 32.
PAGE 19
Data Sheet AD5123/AD5143 THEORY OF OPERATION The AD5123/AD5143 digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data.
PAGE 20
AD5123/AD5143 Data Sheet Table 9.
PAGE 21
Data Sheet AD5123/AD5143 ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5123/AD5143 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 15 and Table 17). The AD5123/AD5143 include two commands to reduce the wiper resistance between the terminals when the devices achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS.
PAGE 22
AD5123/AD5143 Data Sheet ±6 dB Increment and Decrement Instructions Reset Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the −6 dB decrement is activated by Command 7 (see Table 15).
PAGE 23
Data Sheet AD5123/AD5143 Table 15.
PAGE 24
AD5123/AD5143 Data Sheet Table 17.
PAGE 25
Data Sheet AD5123/AD5143 RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5123/AD5143 employ a three-stage segmentation approach, as shown in Figure 36. The AD5123/AD5143 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS.
PAGE 26
AD5123/AD5143 Data Sheet VDD In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 Ω is present. Regardless of which setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B, to the maximum continuous current of ±6 mA or to the pulse current specified in Table 5. Otherwise, degradation or possible destruction of the internal switch contact can occur.
PAGE 27
Data Sheet AD5123/AD5143 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E 3.10 3.00 SQ 2.90 Figure 41.
PAGE 28
AD5123/AD5143 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10878-0-3/13(A) Rev.