Datasheet

AD5123/AD5143 Data Sheet
Rev. A | Page 10 of 28
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BITS
DB8DB15 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
ADDRESS BITS
A0A1
A2C2 C1 C0 A3C3
CONTROL BITS
DB7
10878-002
Figure 2. Input Shift Register Contents
t
7
t
6
t
2
t
4
t
11
t
12
t
6
t
5
t
10
t
1
SCL
SD
A
PS S P
t
3
t
8
t
9
10878-003
Figure 3. I
2
C Serial Interface Timing Diagram (Typical Write Sequence)