Datasheet

Data Sheet AD5123/AD5143
Rev. A | Page 19 of 28
THEORY OF OPERATION
The AD5123/AD5143 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of V
SS
< V
TERM
< V
DD
. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
register) can be used to preload the RDAC register data.
The RDAC register can be programmed with any position setting
using the I
2
C interface (depending on the model). When a desirable
wiper position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-ups. The storing of EEPROM
data takes approximately 15 ms; during this time, the device is
locked and does not acknowledge any new command, preventing
any changes from taking place.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5143, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 9).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 9). Thereafter, the RDAC register
always sets at that position for any future on-off-on power supply
sequence. It is possible to read back data saved into the EEPROM
with Command 3 (see Table 9).
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 15).
INPUT SHIFT REGISTER
For the AD5123/AD5143, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits.
If the AD5143 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 9 and
Table 15.
I
2
C SERIAL DATA INTERFACE
The AD5123/AD5143 has 2-wire, I
2
C-compatible serial interfaces.
These devices can be connected to an I
2
C bus as a slave device,
under the control of a master device. See Figure 3 for a timing
diagram of a typical write sequence.
The AD5123/AD5143
supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/
W
bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
If the R/
W
bit is set high, the master reads from the slave
device. However, if the R/
W
bit is set low, the master writes
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
I
2
C ADDRESS
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus as
outlined in Table 8.
Table 8. I
2
C Address Selection
ADDR Pin 7-Bit I
2
C Device Address
V
DD
0101000
No connect
1
0101010
GND 0101011
1
Not available in bipolar mode ( V
SS
< 0 V).