Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Permanent LFCSP 10 WD

Single-Channel, 1024-Position, Digital Rheostat

with I

C Interface and 50-TP Memory

AD5175

Rev. A

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FEATURES

Single-channel, 1024-position resolution

10 kΩ nominal resistance

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation

±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations

C-compatible interface

Wiper setting and memory readback

Power on refreshed from memory

Resistor tolerance stored in memory

Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package

Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage to current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

FUNCTIONAL BLOCK DIAGRAM

AD5175

SCL

ADDR

SDA

SERIAL

INTERFACE

POWER-ON

RESET

RDAC

50-TP

MEMORY

BLOCK

RESET

EXT_CAP GND

08719-001

Figure 1.

GENERAL DESCRIPTION

The AD5175 is a single-channel, 1024-position digital rheostat

that combines industry leading variable resistor performance

with nonvolatile memory (NVM) in a compact package.

This device supports both dual-supply operation at ±2.5 V to

±2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers

50-times programmable (50-TP) memory.

The AD5175 device wiper settings are controllable through the

C–compatible digital interface. Unlimited adjustments are

allowed before programming the resistance value into the

50-TP memory. The AD5175 does not require any external

voltage supply to facilitate fuse blow and there are 50 oppor-

tunities for permanent programming. During 50-TP activation,

a permanent blow fuse command freezes the resistance position

(analogous to placing epoxy on a mechanical rheostat).

The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP

package and in a 10-lead MSOP package. The part is guaranteed

to operate over the extended industrial temperature range of

−40°C to +125°C.

Summary of content (20 pages)

PAGE 1
Single-Channel, 1024-Position, Digital Rheostat with I2C Interface and 50-TP Memory AD5175 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET RDAC REGISTER SCL SDA I2C SERIAL INTERFACE A 10 W 50-TP MEMORY BLOCK ADDR RESET VSS APPLICATIONS AD5175 EXT_CAP GND 08719-001 Single-channel, 1024-position resolution 10 kΩ nominal resistance 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 35 ppm/°C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.
PAGE 2
AD5175 TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 12 Applications ....................................................................................... 1 Write Operation.......................................................................... 13 Functional Block Diagram ..........................................................
PAGE 3
AD5175 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Symbol Test Conditions/Comments Min R-INL |VDD − VSS| = 3.6 V to 5.5 V |VDD − VSS| = 3.3 V to 3.6 V |VDD − VSS| = 2.7 V to 3.
PAGE 4
AD5175 Parameter DYNAMIC CHARACTERISTICS4, 10 Bandwidth Total Harmonic Distortion Resistor Noise Density Symbol Test Conditions/Comments −3 dB, RAW = 5 kΩ, Terminal W, see Figure 23 VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ RWB = 5 kΩ, TA = 25°C, f = 10 kHz Min Typ 1 700 −90 13 Max Unit kHz dB nV/√Hz 1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
PAGE 5
AD5175 Parameter tRDAC_R-PERF tRDAC_NORMAL tMEMORY_READ tMEMORY_PROGRAM tRESET tPOWER-UP 6 Limit at TMIN, TMAX Min Max 2 600 6 350 600 2 Conditions 1 Unit μs ns μs ms μs ms Description RDAC register write command execute time (R-Perf mode) RDAC register write command execute time (normal mode) Memory readback execute time Memory program time Reset 50-TP restore time Power-on 50-TP restore time 1 Maximum bus capacitance is limited to 400 pF.
PAGE 6
AD5175 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Pulsed 1 Frequency > 10 kHz Frequency ≤ 10 kHz Continuous Operating Temperature Range 3 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V +0.3 V to −7.0 V 7V VSS − 0.3 V, VDD + 0.3 V −0.
PAGE 7
AD5175 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 ADDR VDD 1 A 2 W 3 VSS 4 10 ADDR 9 SCL 8 SDA 7 RESET 6 GND AD5175 TOP VIEW (Not to Scale) EXT_CAP 5 EXT_CAP 5 9 SCL 8 SDA W 3 VSS 4 08719-004 VDD 1 AD5175 (EXPOSED PAD)* 7 RESET 6 GND *LEAVE FLOATING OR CONNECTED TO VSS. Figure 4. MSOP Pin Configuration 08719-103 A 2 Figure 5. LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No.
PAGE 8
AD5175 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.7 +25°C –40°C +125°C 0.6 VDD/VSS = 5V/0V 0.6 0.5 CURRENT (mA) 0.2 0 –0.2 0.4 0.3 0.2 0.1 –0.4 0 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.1 08719-014 –0.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOLTAGE (V) 08719-038 INL (LSB) 0.4 Figure 9. Supply Current (IDD) vs. Digital Input Voltage Figure 6. R-INL in Normal Mode vs. Code vs. Temperature 500 0.4 +25°C –40°C +125°C 0.
PAGE 9
AD5175 0 –20 –5 0x200 –10 0x100 –25 VDD/VSS = 5V/0V CODE = HALF SCALE –30 –15 0x080 –35 PSRR (dB) GAIN (dB) –20 0x040 –25 0x020 –30 0x010 –40 –45 –45 0x008 –50 0x004 0x002 –55 0x001 VDD/VSS = 5V/0V –50 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) –60 10 08719-031 –40 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Bandwidth vs. Frequency vs. Code 08719-024 –35 Figure 15. PSRR vs. Frequency 8 0 VDD/VSS = ±2.
PAGE 10
AD5175 1.0 0.006 VDD/VSS = 5V/0V IAW = 10µA CODE = HALF SCALE 0.005 ΔRAW RESISTANCE (%) 0 –0.5 0.004 0.003 0.002 0.001 0 –1.0 0 10 20 30 40 TIME (µs) 50 60 –0.002 Figure 18. Digital Feedthrough 0 100 200 300 400 500 600 700 800 900 1000 OPERATION AT 150°C (Hours) Figure 19. Long-Term Drift Accelerated Average by Burn-In Rev. A | Page 10 of 20 08719-101 –1.5 –10 –0.001 VDD/VSS = ±2.5V IAW = 200µA 08719-100 VOLTAGE (mV) 0.
PAGE 11
AD5175 TEST CIRCUITS Figure 20 to Figure 24 define the test conditions used in the Specifications section. DUT DUT IW 1GΩ W W A VMS 08719-033 VMS Figure 23. Gain vs. Frequency Figure 20. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT RWA = CODE = 0x00 DUT IW RW = V 08719-036 A VMS IW GND ICM W +2.75V –2.75V RWA A 2 GND W NC = NO CONNECT +2.75V Figure 21. Wiper Resistance V+ = VDD ±10% IW W V+ PSS (%/%) = –2.75V Figure 24.
PAGE 12
AD5175 THEORY OF OPERATION The AD5175 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface.
PAGE 13
AD5175 Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the AD5175. A stop condition follows. The write operations for the AD5175 are shown in Figure 25. WRITE OPERATION It is possible to write data for the RDAC register or the control register.
PAGE 14
AD5175 1 9 1 9 SCL 0 1 0 1 1 A1 A0 R/W START BY MASTER 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD5175 ACK. BY AD5175 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 9 1 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5175 FRAME 3 LEAST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) 0 SDA (CONTINUED) 0 C3 C2 C1 C0 D9 D8 ACK.
PAGE 15
AD5175 READ OPERATION which enables readback of the RDAC register, 50-TP memory, or the control register. The user can then read back the data beginning with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, as shown in Figure 27. A stop condition follows. If the master does not acknowledge the first byte, the second byte is not transmitted by the AD5175.
PAGE 16
AD5175 Prior to 50-TP activation, the AD5175 presets to midscale on power-up. It is possible to read back the contents of any of the 50-TP memory registers through the I2C interface by using Command 5 in Table 7. The lower six LSB bits, D0 to D5 of the data byte, select which memory location is to be read back. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 in Table 7.
PAGE 17
AD5175 Table 8. Write and Read to RDAC and 50-TP Memory DIN 0x1C03 0x0500 0x0800 0x0C00 SDO1 0xXXXX 0x1C03 0x0500 0x100 0x1800 0x0000 0x0C00 0xXX19 0x1419 0x2000 0x0000 0x0100 0x0000 0xXXXX 1 Action Enable update of wiper position and 50-TP memory contents through digital interface. Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position. Prepare data read from RDAC register. Stores RDAC register content into 50-TP memory.
PAGE 18
AD5175 50-TP MEMORY WRITE-ACKNOWLEDGE POLLING RDAC ARCHITECTURE After each write operation to the 50-TP registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition followed by the slave address and the write bit.
PAGE 19
AD5175 Calculate the Actual End-to-End Resistance TERMINAL VOLTAGE OPERATING RANGE The resistance tolerance is stored in the internal memory during factory testing. The actual end-to-end resistance can, therefore, be calculated (which is valuable for calibration, tolerance matching, and precision applications). The positive VDD and negative VSS power supplies of the AD5175 define the boundary conditions for proper 2-terminal digital resistor operation.
PAGE 20
AD5175 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 PIN 1 INDEX AREA 10 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.25 0.20 0.20 REF 121009-A SEATING PLANE 1 BOTTOM VIEW Figure 31.