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Table Of Contents

Quad, 15 V, 256-

Position, Digital

Potentiometer with Pin-Selectable SPI/I

Data Sheet

AD5263

Rev. F Document Feedback

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FEATURES

256-position, 4-channel

End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ

Pin-selectable SPI®- or I

C®-compatible interface

Power-on preset to midscale

Two package address decode pins AD0 and AD1

Rheostat mode temperature coefficient 30 ppm/°C

Voltage divider temperature coefficient 5 ppm/°C

Wide operating temperature range –40°C to +125°C

10 V to 15 V single supply; ±5 V dual supply

APPLICATIONS

Mechanical potentiometer replacement

Optical network adjustment

Instrumentation: gain, offset adjustment

Stereo channel audio level control

Automotive electronics adjustment

Programmable power supply

Programmable filters, delays, time constants

Line impedance matching

Low resolution DAC/trimmer replacement

Base station power amp biasing

Sensor calibration

FUNCTIONAL BLOCK DIAGRAM

03142-001

SERIAL INPUT

AD5263

ADDRESS

DECODER

SPI/I

SELECT

LOGIC

GND

W1 B1 A2

W2 B2

B3 A4

CS/AD0

SDI/SDA

CLK/SCL

SHDN

RES/AD1

DIS

NC/O2

SDO/O1

RDAC 1

RDAC 2

RDAC 3

RDAC 4

Figure 1.

GENERAL DESCRIPTION

The AD5263 is the industry’s first quad-channel, 256-position,

digital potentiometer

with a selectable digital interface. This

device performs the same electronic adjustment function as

mechanical potentiometers or variable resistors, with enhanced

resolution, solid-state reliability, and superior low temperature

coefficient performance.

Each channel of the AD5263 offers a completely programmable

value of resistance between the A terminal and the wiper or

between the B terminal and the wiper. The fixed A-to-B

terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal

temperature coefficient of ±30 ppm/°C and a ±1% channel-to-

channel matching tolerance. Another key feature of this part is

the ability to operate from +4.5 V to +15 V, or at ±5 V.

Wiper position programming presets to midscale upon power-

on. Once powered, the VR wiper position is programmed by

either the 3-wire SPI or 2-wire I

C-compatible interface. In the

C mode, additional programmable logic outputs enable users

to drive digital loads, logic gates, and analog switches in their

systems.

The AD5263 is available in a narrow body, 24-lead TSSOP.

All parts are guaranteed to operate over the automotive

temperature range of –40°C to +125°C.

For single- or dual-channel applications, refer to the

AD5260/AD5280 or AD5262/AD5282 data sheets.

The terms digital potentiometer, VR, and RDAC are used interchangeably.

Summary of content (28 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position, 4-channel End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ Pin-selectable SPI®- or I2C®-compatible interface Power-on preset to midscale Two package address decode pins AD0 and AD1 Rheostat mode temperature coefficient 30 ppm/°C Voltage divider temperature coefficient 5 ppm/°C Wide operating temperature range –40°C to +125°C 10 V to 15 V single supply; ±5 V dual supply A1 B1 A2 W2 B2 A3 W3 B3 A4 W4 B4 VSS SHDN RES/AD1 RDAC 1 REGISTER RDAC 2 REGISTER GN
PAGE 2
AD5263 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Multiple Devices on One Bus ................................................... 21 Applications ....................................................................................... 1 Level Shift for Negative Voltage Operation ................................ 21 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD5263 ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted. Table 1.
PAGE 4
AD5263 Parameter POWER SUPPLIES Logic Supply 8 Power Single-Supply Range Power Dual-Supply Range Logic Supply Current 9 Positive Supply Current Negative Supply Current Power Dissipation 10 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 11 Bandwidth (3 dB) Total Harmonic Distortion Data Sheet Symbol VL VDD RANGE VDD/SS RANGE IL IDD ISS PDISS PSS BW THDW VW Settling Time 12 tS Resistor Noise Voltage eN_WB Conditions Min VSS = 0 V 2.7 4.5 ±4.
PAGE 5
Data Sheet AD5263 TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted. Table 2.
PAGE 6
AD5263 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VL to GND VA, VB, VW to GND Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx Pulsed1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance2 θJA TSSOP-24 Value −0.3 V to +16.5 V −7.5 V to 0 V +16.5 V −0.3 V to +6.
PAGE 7
Data Sheet AD5263 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS B1 1 24 B2 A1 2 23 A2 W1 3 22 W2 AD5263 B4 TOP VIEW A3 5 (Not to Scale) 20 A4 19 W4 W3 6 21 VDD 7 18 VSS GND 8 17 NC/O2 DIS 9 16 SDO/O1 VLOGIC 10 15 SHDN SDI/SDA 11 14 RES/AD1 CLK/SCL 12 13 CS/AD0 03142-072 B3 4 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin 1 2 3 4 5 6 7 Name B1 A1 W1 B3 A3 W3 VDD Description Resistor Terminal B1. Resistor Terminal A1 (ADDR = 00). Wiper Terminal W1.
PAGE 8
AD5263 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS RAB = 20 kΩ, unless otherwise noted. 1.0 1.0 ±5V 0.8 –40°C +25°C +85°C +125°C 0.8 RHEOSTAT MODE INL (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 0.6 0.4 0.2 0 –0.2 –0.4 –0.8 –1.0 0 32 64 96 128 160 192 224 03142-004 –0.6 –0.6 03142-073 RHEOSTAT MODE DNL (LSB) +15/0V –0.8 –1.0 0 256 32 64 CODE (Decimal) 224 256 1.0 1.0 ±5V +15/0V 0.8 0.6 POTENTIOMETER MODE INL (LSB) ±5V +15/0V 0.4 0.2 0 –0.2 –0.4 03142-002 –0.6 –0.8 –1.
PAGE 9
Data Sheet AD5263 2.0 1.0 –40°C +25°C +85°C +125°C 0.6 VDD/VSS = +4.5/0V 1.8 1.6 0.4 1.4 0.2 1.2 0 –0.2 1.0 0.8 –0.4 0.6 –0.6 0.4 –0.8 0 64 32 96 128 160 192 224 0.2 0 –40 256 –20 0 CODE (Decimal) Figure 9. INL vs. Code; VDD = ±5 V 120 VLOGIC = 5V VIH = 5V VIL = 0V 0.2 0 –0.2 –0.4 –0.6 –0.8 0 32 64 96 128 160 192 224 1 ISS @ VDD/VSS = ±5V 0.1 IDD @ VDD/VSS = +15/0V 0.01 IDD @ VDD/VSS = ±5V 0.
PAGE 10
AD5263 Data Sheet 150 ILOGIC (µA) VDD/VSS = +15/0V 25 VDD/VSS = ±5V 24 03142-013 23 22 –40 0 40 80 50 0 –50 –100 –150 –200 –250 120 20kΩ 50kΩ 200kΩ 100 03142-016 26 POTENTIOMETER MODE TEMPCO (ppm/°C) 27 0 32 64 96 TEMPERATURE (°C) Figure 15. ILOGIC vs. Temperature 160 192 224 256 Figure 18. Potentiometer Mode Tempco ∆RWB/∆T vs.
PAGE 11
Data Sheet AD5263 0 0x80 –6 –12 0x20 –18 0x10 –24 0x08 –30 VW 1 0x04 –36 0x02 –42 0x01 TA = 25°C VA = 50mV rms VDD/VSS = ±5V –54 –60 1k 10k 03142-022 –48 03142-0-019 GAIN (dB) CODE = 0x80 VDD/VSS = ±5.5V VB/VA= ±5V 0x40 CH1 50.0mV 100k M100ns A CH2 2.70V FREQUENCY (Hz) Figure 24. Digital Feedthrough Figure 21. Gain vs. Frequency vs.
PAGE 12
AD5263 Data Sheet 1.0 2.0 RAB = 20kΩ TA = 25°C 1.0 R-INL (LSB) Avg – 3σ Avg Avg – 3σ 0 –0.5 0.5 Avg – 3σ Avg Avg – 3σ 0 –0.5 –1.0 0 5 10 |VDD – VSS| (–V) 15 –2.0 20 Figure 27. INL vs. Supply Voltage 03142-026 –1.5 03142-025 INL (LSB) 0.5 –1.0 RAB = 20kΩ TA = 25°C 1.5 0 5 10 |VDD – VSS| (V) 15 Figure 28. R-INL vs. Supply Voltage Rev.
PAGE 13
Data Sheet AD5263 TEST CIRCUITS Figure 29 to Figure 39 define the test conditions used in the Electrical Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions section and the Timing Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions. A DUT B 5V W W OP279 B VMS OFFSET GND Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) VOUT 03142-032 V+ DUT VIN 03142-028 A V+ = VDD 1LSB = V+/2N OFFSET BIAS Figure 33.
PAGE 14
AD5263 Data Sheet A VSS GND B W N/C ICM W1 A2 RDAC 2 W2 VIN B1 VCM 03142-036 VDD DUT VDD NC VSS CTA = 20 log [VOUT/VIN] Figure 37. Test Circuit for Common-Mode Leakage Current VOUT B2 03142-038 A1 RDAC 1 NC Figure 39. Test Circuit for Analog Crosstalk ILOGIC VLOGIC SCL 03142-037 SCA Figure 38. Test Circuit for VLOGIC Current vs. Digital Input Voltage Rev.
PAGE 15
Data Sheet AD5263 SPI-COMPATIBLE DIGITAL INTERFACE (DIS = 0) SERIAL DATA-WORD FORMAT Addr B9 A1 29 B8 A0 MSB Data B7 D7 27 LSB B6 D6 B5 D5 1 CLK CS VOUT 0 1 A1 A0 D7 D6 0 1 D5 D4 B3 D3 D3 D2 D1 B2 D2 B1 D1 B0 D0 20 D0 RDAC REGISTER LOAD 0 1 03142-039 SDI B4 D4 0 Figure 40. AD5263 Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 tCH tDS tCS1 tCH 1 CLK 0 tCSHO tCL tCSH1 tCSS 1 CS tC-SW 0 tS 0 ±LSB Figure 41.
PAGE 16
AD5263 Data Sheet I2C-COMPATIBLE DIGITAL INTERFACE (DIS = 1) The word format maps in this section use the following abbreviations. Abbreviation S P A AD1, AD0 A1, A0 RS SD Description Start condition. Stop condition. Acknowledge. I2C device address bits. Must match with the logic states at Pin AD1 and Pin AD0. Refer to Figure 49. RDAC channel select. Software reset wiper (A1, A0) to midscale position.
PAGE 17
Data Sheet AD5263 OPERATION The AD5263 is a quad-channel, 256-position, digitally controlled, variable resistor (VR) device. To program the VR settings, refer to the SPI-Compatible Digital Interface (DIS = 0) section and the I2C-Compatible Digital Interface (DIS = 1) section. The part has an internal power-on preset that places the wiper at midscale during power-on, simplifying the fault condition recovery at power-up.
PAGE 18
AD5263 Data Sheet The typical distribution of the end-to-end resistance RAB from channel to channel matches within ±1%. Device-to-device matching is process-lot dependent, and it is possible to have ±30% variation. Because the resistance element is processed in thin film technology, the change in RAB with temperature has a very low temperature coefficient of 30 ppm/°C.
PAGE 19
Data Sheet AD5263 Daisy-Chain Operation The serial data output (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the SDI pin of the next package. This allows for daisy-chaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be greater than the VDD supply voltage.
PAGE 20
AD5263 In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 44).
PAGE 21
Data Sheet AD5263 +5V Figure 49 shows four AD5263 devices on the same serial bus. Each has a different slave address because the states of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain, pull-downs in a fully I2C-compatible interface. 0V VIN R3 1kΩ Q1 2N3906 Q2 2N3906 VOUT R2 10kΩ R1 10kΩ 0V –5V –5V +5V 03142-051 MULTIPLE DEVICES ON ONE BUS –5V Figure 51.
PAGE 22
AD5263 Data Sheet VLOGIC POWER SUPPLY RDAC CIRCUIT SIMULATION MODEL The AD5263 is capable of operating at high voltages beyond the internal logic levels, which are limited to operation at 5 V. As a result, VL always needs to be tied to a separate 2.7 V to 5.5 V source to ensure proper digital signal levels. Logic levels must be limited to VL, regardless of VDD. In addition, VL should always be less than or equal to VDD.
PAGE 23
Data Sheet AD5263 APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5263 can be operated from dual supplies, enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across Terminal A to Terminal B, with the output taken from Terminal W. +5.0V VDD VDD µC SCLK SCL GND MCSI SDA A1 ±5V p-p ±2.
PAGE 24
AD5263 Data Sheet 8-BIT BIPOLAR DAC Figure 60 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps, but not the precision as compared to conventional DACs. The linearity and temperature coefficient, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is (4) +15V VI OP2177 VO A2 B 1 U1 –15V –5VREF VOUT +5VREF ADR425 TRIM 0 64 128 192 255 +15V GND V+ OP2177 V– Figure 60.
PAGE 25
Data Sheet AD5263 PROGRAMMABLE 4 TO 20 MA CURRENT SOURCE A programmable 4–20 mA current source can be implemented with the circuit shown in Figure 63. The REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at +2.048 V.
PAGE 26
AD5263 Data Sheet PROGRAMMABLE LOW-PASS FILTER At resonance, setting In analog-to-digital conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. Dual-channel digital potentiometers can be used to construct a second-order Sallen-Key low-pass filter (see Figure 65). The design equations are VI = ωO = Q= ωO 2 ωO S2 + (10) S + ωO 2 Q 1 R1 × R2 × C1 × C2 (11) 1 1 + R1 × C1 R2 × C2 balances the bridge.
PAGE 27
Data Sheet AD5263 The AD5263 offers 20 kΩ, 50 kΩ, and 200 kΩ nominal resistances. Users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 67 shows a simple scheme of using two channels in parallel. To adjust half of the resistance linearly per step, users need to program both channels to the same settings. VDD A1 A2 W1 B2 W2 03142-066 B1 LED Figure 67.
PAGE 28
AD5263 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 72.