Datasheet

AD5263
Rev. A | Page 19 of 28
of data is required. The first 10 bits, complying with the format
shown in the
Serial Data-Word Format section and bit map, go
to U2 and the second 10 bits, with the same format, go to U1.
CS
should be kept low until all 20 bits are clocked into their
respective serial registers. After this,
CS
is pulled high to
complete the operation and load the RDAC latch. Note that data
appears on SDO on the negative edge of the clock, thus making
it available to the input of the daisy-chained device on the rising
edge of the next clock.
03142-046
AD5263 AD5263
U2
SPI
U1
SDI
CLK
SDO
CLK
SDI
SDO
MOSI
V
L
R
P
2.2kΩ
CSCLK CS
CS
Figure 47. Daisy-Chain Configuration
I
2
C-COMPATIBLE 2-WIRE SERIAL BUS (DIS = 1)
In the I
2
C-compatible mode, the RDACs are connected to the
bus as slave devices.
Referring to the bit maps in the
I C-Compatible Digital
Interface (DIS = 1)
2
section, the first byte of the AD5263 is a
slave address byte, consisting of a 7-bit slave address and a R/
W
bit. The five MSBs are 01011 and the following two bits are
determined by the state of the AD0 and AD1 pins of the device.
AD0 and AD1 allow the user to place up to four of the I
2
C-
compatible devices on one bus.
The 2-wire I
2
C serial bus protocol operates as follows.
1. The master initiates a data transfer by establishing a
START condition, which is when a high-to-low transition
on the SDA line occurs while SCL is high (see
Figure 43).
The following byte is the slave address byte, which consists
of the 7-bit slave address followed by an R/
W
bit. This R/
W
bit determines whether data will be read from or written to
the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/
W
bit is high, the master reads
from the slave device. If the R/
W
bit is low, the master
writes to the slave device.
2. In write mode, the second byte is the instruction byte. The
first bit (MSB) of the instruction byte is a don’t care. The
following two bits, labeled A1 and A0, are the RDAC
subaddress select bits.
The fourth MSB (RS) is the midscale reset. A logic high on
this bit moves the wiper of the selected channel to the
center tap where RWA = RWB. This feature effectively
writes over the contents of the register, so that when taken
out of reset mode, the RDAC remains at midscale.
The fifth MSB (SD) is the shutdown bit. A logic high
causes the selected channel to open circuit at Terminal A
while shorting the wiper to Terminal B. This operation
yields almost 0 Ω in rheostat mode or 0 V in potentiometer
mode. This SD bit serves the same function as the
SHDN
pin except that the
SHDN
pin reacts to active low. In
addition, the
SHDN
pin affects all channels, as opposed to
the SD bit, which affects only the channel being written to.
It is important to note that the shutdown operation does
not disturb the contents of the register. When brought out
of shutdown, the previous setting is applied to the RDAC.
The next two bits are O2 and O1. They are extra
programmable logic outputs that can be used to drive other
digital loads, logic gates, LED drivers, analog switches, etc.
The LSB is a don’t care bit (see the bit map in the
I C Write
Mode Data-Word Format
2
section).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the SDA
line must occur during the low period of SCL and remain
stable during the high period of SCL (see
Figure 43).
3. In read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where
there are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see
Figure 44).
Note that the channel of interest is the one that was
previously selected in write mode. In cases where users
need to read the RDAC values of both channels, they must
program the first channel in write mode and then change
to read mode to read the first channel value. After that,
they must change back to write mode with the second
channel selected and read the second channel value in read
mode again. It is not necessary for users to issue the
Frame 3 data byte in the write mode for subsequent
readback operation. Refer to
Figure 44 for the
programming format.