Datasheet

AD5263
Rev. A | Page 21 of 28
However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. As a result,
Figure 51 shows one implement-
tation with a couple of transistors and a few resistors. When V
IN
is high, Q1 is turned on and its emitter is clamped at one
threshold above ground. This threshold appears at the base of
Q2, which causes Q2 to turn off. In this state, V
OUT
approaches
−5 V. When V
IN
is low, Q1 is turned off and the base of Q2 is
pulled low, which in turn causes Q2 to turn on. In this state,
V
OUT
approaches 0 V. Beware that proper time shifting is also
needed for successful communication with the device.
03142-051
V
IN
V
OUT
–5V
–5V
Q2
2N3906
Q1
2N3906
+
5
V
0V
–5V
0V
R3
1kΩ
R1
10kΩ
R2
10kΩ
Figure 51. Level Shift for Bipolar Potential Operation
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in
Figure 52 and Figure 53.
This protection applies to digital input pins SDI/SDA, CLK/SCL,
CS
/AD0,
RES
/AD1, and
SHDN
.
LOGIC
340Ω
V
SS
03142-052
Figure 52. ESD Protection of Digital Pins
03142-053
A,B,W
V
SS
Figure 53. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5263 positive V
DD
and negative V
SS
power supply
defines the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed V
DD
or V
SS
are clamped by the
internal forward-biased diodes shown in
Figure 54.
A
V
DD
B
W
V
SS
03142-054
Figure 54. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (see
Figure 54), it is important to
power V
DD
and V
SS
before applying any voltage to the A, B, and
W terminals; otherwise, the diodes are forward biased such that
V
DD
and V
SS
are powered unintentionally and may affect the rest
of the circuit. The ideal power-up sequence is in the following
order: GND, V
DD
, V
SS
, V
L
, digital inputs, and V
A/B/W
. The relative
order of powering V
A
, V
B
, VB
W
, and digital inputs is not
important as long as they are powered after V
DD
and V
SS
.
V
LOGIC
POWER SUPPLY
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, V
L
always needs to be tied to a separate 2.7 V to 5.5 V
source to ensure proper digital signal levels. Logic levels must
be limited to V
L
, regardless of V
DD
. In addition, V
L
should
always be less than or equal to V
DD
.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF ceramic
disc or chip capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see
Figure 55). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
03142-055
GND
V
SS
V
DD
AD5263
V
SS
V
DD
C1
0.1µF
C2
0.1µF
C3
10µF
C4
10µF
+
+
Figure 55. Power Supply Bypassing