Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsLinear IC - Op-amp Programmable gain PDIP 16

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

Software Programmable

Gain Amplifier

AD526

FEATURES

Digitally Programmable Binary Gains from 1 to 16

Two-Chip Cascade Mode Achieves Binary Gain from

1 to 256

Gain Error:

0.01% Max, Gain = 1, 2, 4 (C Grade)

0.02% Max, Gain = 8, 16 (C Grade)

0.5 ppm/ⴗC Drift Over Temperature

Fast Settling Time

10 V Signal Change:

0.01% in 4.5 ␮s (Gain = 16)

Gain Change:

0.01% in 5.6 ␮s (Gain = 16)

Low Nonlinearity: ⴞ0.005% FSR Max (J Grade)

Excellent DC Accuracy:

Offset Voltage: 0.5 mV Max (C Grade)

Offset Voltage Drift: 3 ␮V/ⴗC (C Grade)

TTL-Compatible Digital Inputs

PRODUCT DESCRIPTION

The AD526 is a single-ended, monolithic software program-

mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8

and 16. It is complete, including amplifier, resistor network

and TTL-compatible latched inputs, and requires no external

components.

Low gain error and low nonlinearity make the AD526 ideal for

precision instrumentation applications requiring programmable

gain. The small signal bandwidth is 350 kHz at a gain of 16. In

addition, the AD526 provides excellent dc precision. The FET-

input stage results in a low bias current of 50 pA. A guaranteed

maximum input offset voltage of 0.5 mV max (C grade) and low

gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using

Analog Devices’ laser trimming technology.

To provide flexibility to the system designer, the AD526 can be

operated in either latched or transparent mode. The force/sense

configuration preserves accuracy when the output is connected

to remote or low impedance loads.

The AD526 is offered in one commercial (0°C to +70°C) grade,

J, and three industrial grades, A, B and C, which are specified

from –40°C to +85°C. The S grade is specified from –55°C to

+125°C. The military version is available processed to MIL-

STD 883B, Rev C. The J grade is supplied in a 16-lead plastic

DIP, and the other grades are offered in a 16-lead hermetic

side-brazed ceramic DIP.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

DIG GND A1

AD526

NULL A0

NULL

CLK

ANALOG GND 2 A2

ANALOG GND 1 B

–V

OUT

SENSE V

OUT

FORCE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

ORDERING GUIDE

Temperature Package Package

Model Range Descriptions Options

AD526JN Commercial 16-Lead Plastic DIP N-16

AD526AD Industrial 16-Lead Cerdip D-16

AD526BD Industrial 16-Lead Cerdip D-16

AD526CD Industrial 16-Lead Cerdip D-16

AD526SD Military 16-Lead Cerdip D-16

AD526SD/883B Military 16-Lead Cerdip D-16

5962-9089401MEA* Military 16-Lead Cerdip D-16

*Refer to official DESC drawing for tested specifications.

APPLICATION HIGHLIGHTS

1. Dynamic Range Extension for ADC Systems: A single

AD526 in conjunction with a 12-bit ADC can provide

96 dB of dynamic range for ADC systems.

2. Gain Ranging Preamps: The AD526 offers complete digital

gain control with precise gains in binary steps from 1 to 16.

Additional gains of 32, 64, 128 and 256 are possible by cas-

cading two AD526s.

Summary of content (14 pages)

PAGE 1
a Software Programmable Gain Amplifier AD526 FEATURES Digitally Programmable Binary Gains from 1 to 16 Two-Chip Cascade Mode Achieves Binary Gain from 1 to 256 Gain Error: 0.01% Max, Gain = 1, 2, 4 (C Grade) 0.02% Max, Gain = 8, 16 (C Grade) 0.5 ppm/ⴗC Drift Over Temperature Fast Settling Time 10 V Signal Change: 0.01% in 4.5 ␮s (Gain = 16) Gain Change: 0.01% in 5.6 ␮s (Gain = 16) Low Nonlinearity: ⴞ0.005% FSR Max (J Grade) Excellent DC Accuracy: Offset Voltage: 0.
PAGE 2
AD526–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC unless otherwise noted) S Model Min GAIN Gain Range (Digitally Programmable) Gain Error Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain Error Drift Over Temperature G=1 G=2 G=4 G=8 G = 16 Gain Error (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 VOLTAGE OFFSET, ALL GAINS Input Offset Voltage Input Of
PAGE 3
AD526 Model Min NOISE, ALL GAINS Voltage Noise, RTI 0.1 Hz to 10 Hz Voltage Noise Density, RTI f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz AD526J Typ AD526B/S Typ Max Min AD526C Typ Max Units 3 µV p-p 70 60 30 25 70 60 30 25 70 60 30 25 70 60 30 35 nV√Hz nV√Hz nV√Hz nV√Hz 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.35 4.0 2.0 1.5 0.65 0.
PAGE 4
AD526–Typical Performance Characteristics +258C RL = 2kV 10 5 0 5 10 15 SUPPLY VOLTAGE – 6V Figure 1. Output Voltage Swing vs. Supply Voltage, G = 16 20 @ VS = 615V 10 0 100 20 INPUT BIAS CURRENT – pA 15 0 20 30 OUTPUT VOLTAGE SWING – 6V OUTPUT VOLTAGE SWING – 6V 20 VIN = 0 10 5 0 1k LOAD RESISTANCE – V 10k 0 5 10 15 SUPPLY VOLTAGE – 6V 20 Figure 3. Input Bias Current vs. Supply Voltage Figure 2. Output Voltage Swing vs.
PAGE 5
AD526 0.006 0.004 NONLINEARITY – %FSR INPUT NOISE VOLTAGE – nV/ Hz 1000 100 0.002 0.000 –0.002 10 10 1k 100 10k FREQUENCY – Hz 100k Figure 10. Noise Spectral Density Figure 13. Large Signal Pulse Response and Settling Time,* G=1 Figure 16. Small Signal Pulse Response, G = 2 –0.004 –60 –20 20 60 100 TEMPERATURE – 8C Figure 11. Nonlinearity vs. Temperature, Gain = 1 Figure 14. Small Signal Pulse Response, G = 1 Figure 17.
PAGE 6
AD526 Figure 19. Large Signal Pulse Response and Settling Time,* G = 8 Figure 20. Small Signal Pulse Response, G = 8 Figure 21. Large Signal Pulse Response and Settling Time,* G = 16 –70 –80 –90 –100 10 Figure 22. Small Signal Pulse Response, Gain = 16 10 PHASE DISTORTION – Dedrees TOTAL HARMONIC DISTORTION – dB –60 100 1k 10k FREQUENCY – Hz 100k Figure 23. Total Harmonic Distortion vs. Frequency Gain = 16 5 0 –5 –10 10 100 1k 10k FREQUENCY – Hz 100k Figure 24. Phase Distortion vs.
PAGE 7
AD526 Figure 28. Gain Change Settling Time,* Gain Change 1 to 8 +15V –15V 10mF 10mF + + Figure 29. Gain Change Settling Time,* Gain Change 1 to 16 +15V –15V 10mF + 10mF + TEKTRONIX 7000 SERIES SCOPE 7A13 PREAMP 5MHz BW AD526 G = 16 OP37 900V G = 10 100V + 10mF Vo = 160 3 e p-p +5V SHIELD NOTE: COAX CABLE 1 FT. OR LESS Figure 30. Wideband Noise Test Circuit +15V –15V 10mF 10mF + + DATA DYNAMICS 5109 (OR EQUIVALENT FLAT-TOP PULSE GENERATOR) +15V –15V 1 2 4 8 16 5.6kV 2.8kV 1.
PAGE 8
AD526 THEORY OF OPERATION TRANSPARENT MODE OF OPERATION The AD526 is a complete software programmable gain amplifier (SPGA) implemented monolithically with a drift-trimmed BiFET amplifier, a laser wafer trimmed resistor network, JFET analog switches and TTL compatible gain code latches. In the transparent mode of operation, the AD526 will respond directly to level changes at the gain code inputs (A0, A1, A2) if B is tied high and both CS and CLK are allowed to float low.
PAGE 9
AD526 TIMING AND CONTROL DIGITAL FEEDTHROUGH With either CS or CLK or both held high, the AD526 gain state will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will unavoidably feed through to the analog circuitry within the AD526 causing spikes to occur at the signal output. Table I.
PAGE 10
AD526 GROUNDING AND BYPASSING Proper signal and grounding techniques must be applied in board layout so that specified performance levels of precision data acquisition components, such as the AD526, are not degraded. Utilizing the force and sense outputs of the AD526, as shown in Figure 38, avoids signal drops along etch runs to low impedance loads. Table II. Logic Table for Figure 38 As is shown in Figure 37, logic and signal grounds should be separate.
PAGE 11
AD526 OFFSET NULLING CASCADED OPERATION Input voltage offset nulling of the AD526 is best accomplished at a gain of 16, since the referred-to-input (RTI) offset is amplified the most at this gain and therefore is most easily trimmed. The resulting trimmed value of RTI voltage offset typically varies less than 3 µV across all gain ranges. A cascade of two AD526s can be used to achieve binarily weighted gains from 1 to 256. If gains from 1 to 128 are needed, no additional components are required.
PAGE 12
AD526 FLOATING-POINT CONVERSION High resolution converters are used in systems to obtain high accuracy, improve system resolution or increase dynamic range. There are a number of high resolution converters available with throughput rates of 66.6 kHz that can be purchased as a single component solution; however in order to achieve higher throughput rates, alternative conversion techniques must be employed. A floating point A/D converter can improve both throughput rate and dynamic range of a system.
PAGE 13
AD526 HIGH ACCURACY A/D CONVERTERS Very high accuracy and high resolution floating-point A/D converters can be achieved by the incorporation of offset and gain calibration routines. There are two techniques commonly used for calibration, a hardware circuit as shown in Figure 43 and/or a software routine. In this application the microprocessor is functioning as the autoranging circuit, requiring software overhead; therefore, a hardware calibration technique was applied which reduces the software burden.
PAGE 14
AD526 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP Package (N-16) 16-Lead Sided-Brazed Ceramic Package (D-16) 0.87 (22.1) MAX 1 8 PIN 1 0.18 (4.57) 0.018 (0.46) 0.100 (2.54) 0.033 (0.84) 0.040R 16 0.310 ⴞ0.01 (7.874 ⴞ0.254) 0.3 (7.62) 0.035 (0.89) 0.125 (3.18) MIN 0.430 (10.922) 0.25 0.31 (6.25) (7.87) 9 0.265 0.290 ⴞ0.010 (6.73) (7.37 ⴞ0.254) 1 0.18 (4.57) MAX 8 PIN 1 0.800 ⴞ0.010 (20.32 ⴞ0.254) 0.011 (0.28) 0.035 ⴞ0.01 (0.889 ⴞ0.254) SEATING PLANE 0.