Datasheet

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16-Bit, Serial Input,

Loop-Powered, 4 mA to 20 mA DAC

Data Sheet

AD5421

Rev. G

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FEATURES

16-bit resolution and monotonicity

Pin selectable NAMUR-compliant ranges

4 mA to 20 mA

3.8 mA to 21 mA

3.2 mA to 24 mA

NAMUR-compliant alarm currents

Downscale alarm current = 3.2 mA

Upscale alarm current = 22.8 mA/24 mA

Total unadjusted error (TUE): 0.05% maximum

INL error: 0.0035% FSR maximum

Output TC: 3 ppm/°C typical

Quiescent current: 300 µA maximum

Flexible SPI-compatible serial digital interface

with Schmitt triggered inputs

On-chip fault alerts via FAULT pin or alarm current

Automatic readback of fault register on each write cycle

Slew rate control function

Gain and offset adjust registers

On-chip reference TC: 4 ppm/°C maximum

Selectable regulated voltage output

Loop voltage range: 5.5 V to 52 V

Temperature range: −40°C to +105°C

TSSOP and LFCSP packages

APPLICATIONS

Industrial process control

4 mA to 20 mA loop-powered transmitters

Smart transmitters

HART network connectivity

GENERAL DESCRIPTION

The AD5421 is a complete, loop-powered, 4 mA to 20 mA

digital-to-analog converter (DAC) designed to meet the needs

of smart transmitter manufacturers in the industrial control

industry. The DAC provides a high precision, fully integrated,

low cost solution in compact TSSOP and LFCSP packages.

The AD5421 includes a regulated voltage output that is used to

power itself and other devices in the transmitter. This regulator

provides a regulated 1.8 V to 12 V output voltage. The AD5421

also contains 1.22 V and 2.5 V references, thus eliminating the

need for a discrete regulator and voltage reference.

The AD5421 can be used with standard HART® FSK protocol

communication circuitry without any degradation in specified

performance. The high speed serial interface is capable of opera-

ting at 30 MHz and allows for simple connection to commonly

used microprocessors and microcontrollers via a SPI-compatible,

3-wire interface.

The AD5421 is guaranteed monotonic to 16 bits. It provides

0.0015% integral nonlinearity, 0.0012% offset error, and

0.0006% gain error under typical conditions.

The AD5421 is available in a 28-lead TSSOP and a 32-lead LFCSP

specified over the extended industrial temperature range of

−40°C to +105°C.

COMPANION LOW POWER PRODUCTS

HART Modem: AD5700, AD5700-1

Microcontroller: ADuCM360

FUNCTIONAL BLOCK DIAGRAM

SET

24kΩ

SYNC

SCLK

SDIN

SDO

LDAC

RANGE0

RANGE1

ALARM_CURRENT_DIRECTION

FAULT

INT

EXT

INPUT

CONTROL

LOGIC

GAIN/OFFSET

ADJUSTMENT

REGISTERS

TEMPERATURE

SENSOR

REFOUT2 REFIN C

EXT1

EXT2

REFOUT1

VREF

16-BIT

DAC

LOOP

VOLTAGE

MONITOR

LOOP

IODV

AD5421

VOLTAGE

REGULATOR

REG_SEL0 REG_SEL1 REG_SEL2 REG

OUT

REG

DRIVE

LOOP–

11.5kΩ 52Ω

09128-001

COM

Figure 1.

Summary of content (36 pages)

PAGE 1
6-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC AD5421 Data Sheet FEATURES GENERAL DESCRIPTION 16-bit resolution and monotonicity Pin selectable NAMUR-compliant ranges 4 mA to 20 mA 3.8 mA to 21 mA 3.2 mA to 24 mA NAMUR-compliant alarm currents Downscale alarm current = 3.2 mA Upscale alarm current = 22.8 mA/24 mA Total unadjusted error (TUE): 0.05% maximum INL error: 0.
PAGE 2
AD5421 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 On-Chip ADC ............................................................................ 23 Applications ....................................................................................... 1 Voltage Regulator ....................................................................... 23 General Description ........................................................
PAGE 3
Data Sheet AD5421 REVISION HISTORY 12/11—Rev. B to Rev. C 10/13—Rev. F to Rev. G Added Figure 4; Renumbered Sequentially ................................. 10 Change to Table 7 ............................................................................ 11 Changes to Fault Alerts Section .................................................... 21 Added Table 11; Renumbered Sequentially ................................. 24 Moved Figure 48 ........................................................................
PAGE 4
AD5421 Data Sheet SPECIFICATIONS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 5
Data Sheet Parameter 1 Gain Error TC3 Full-Scale Error Full-Scale Error TC3 Downscale Alarm Current Upscale Alarm Current OUTPUT CHARACTERISTICS3 Loop Compliance Voltage 4 AD5421 Min 3.08 22.78 3.21 23 Unit ppm FSR/°C % FSR % FSR ppm FSR/°C mA mA 23.99 24.01 mA −0.047 −0.028 +0.047 +0.028 100 V V ppm FSR 15 ppm FSR 1.2 µA/mA 2 75 2.498 Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Output Voltage Drift vs.
PAGE 6
AD5421 Parameter 1 REGOUT OUTPUT Output Voltage Output Voltage TC3 Output Voltage Accuracy Externally Available Current3, 6 Data Sheet Min 1.8 −4 3.
PAGE 7
Data Sheet Parameter1 POWER REQUIREMENTS REGIN IODVDD Quiescent Current AD5421 Min Typ Max Unit Test Conditions/Comments V V μA With respect to LOOP− With respect to COM 260 52 5.5 300 5.5 1.71 1 Temperature range: −40°C to +105°C; typical at +25°C. Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421. System level total error can be reduced using the offset and gain registers.
PAGE 8
AD5421 Data Sheet Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 9
Data Sheet AD5421 AC PERFORMANCE CHARACTERISTICS Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1 DYNAMIC PERFORMANCE Loop Current Settling Time Loop Current Slew Rate AC Loop Voltage Sensitivity 1 Min Typ Max 50 400 1.3 Unit Test Conditions/Comments µs µA/µs µA/V To 0.1% FSR, CIN = open circuit CIN = open circuit 1200 Hz to 2200 Hz, 5 V p-p, RL = 3 kΩ Temperature range: −40°C to +105°C; typical at +25°C.
PAGE 10
AD5421 Data Sheet Timing Diagrams t1 t12 SCLK 1 8 2 9 11 10 t3 SDIN D23 D16 t4 D15 22 12 24 23 t2 D14 D0 D1 D2 D13 t8 t7 t13 D15 SDO t6 D14 D13 D2 D1 D0 t5 t11 SYNC t10 09128-002 t9 LDAC Figure 2. Serial Interface Timing Diagram SCLK SDIN 1 8 9 D23 D16 D15 24 D0 1 8 D23 D16 9 24 D15 D0 NOP OR REGISTER ADDRESS INPUT WORD SPECIFIES REGISTER TO BE READ D15 SDO D0 SPECIFIED REGISTER DATA CLOCKED OUT SYNC Figure 3.
PAGE 11
Data Sheet AD5421 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 6.
PAGE 12
AD5421 Data Sheet IODVDD 1 SYNC SCLK SDO IODVDD REGOUT REGIN DRIVE NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 27 REGIN SCLK 3 26 DRIVE SYNC 4 32 31 30 29 28 27 26 25 28 REGOUT SDO 2 25 VLOOP LDAC 6 TOP VIEW (Not to Scale) 24 LOOP– SDIN LDAC FAULT COM DVDD ALARM CURRENT DIRECTION RINT/REXT RANGE 0 23 REXT2 22 REXT1 FAULT 7 20 REFOUT1 RINT/REXT 10 19 REFOUT2 RANGE0 11 18 REFIN RANGE1 12 17 REG_SEL0 COM 13 16 REG_SEL1 COM 14 15 REG_SEL2 NOTES 1.
PAGE 13
Data Sheet TSSOP 13, 14 Pin No. LFCSP 4, 11, 12 AD5421 Mnemonic COM 15, 16, 17 13, 14, 15 18 19 17 18 REG_SEL2, REG_SEL1, REG_SEL0 REFIN REFOUT2 20 19 REFOUT1 21 20 CIN 22, 23 21, 22 REXT1, REXT2 24 23 LOOP− 25 23 VLOOP 26 26 DRIVE 27 27 REGIN 28 28 REGOUT N/A 1 EPAD 9, 16, 25 EPAD NC Exposed Pad 1 Description Ground Reference Pin for the AD5421. It is recommended that a 4.7 V Zener diode be placed between the LOOP− and COM pins.
PAGE 14
AD5421 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.015 EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET 0.8 0.010 OFFSET ERROR (% FSR) 0.4 0.2 0 –0.2 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C 4mA TO 20mA RANGE EXT VREF EXT RSET –0.4 –0.6 –0.8 –1.0 0 10k 20k 0.005 0 –0.005 30k 40k 50k 60k DAC CODE VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS –0.010 –40 09128-005 –15 60 85 Figure 10. Offset Error vs. Temperature 1.0 0.03 0.8 0.02 0.
PAGE 15
Data Sheet AD5421 0.5 0.0006 MAX INL 0.4 0.0004 0.3 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω 0.1 0 –0.1 MIN DNL –0.2 –0.3 0.0002 0 MIN INL –0.0002 RLOAD = 250Ω TA = 25°C 3.8mA TO 21mA RANGE EXT VREF EXT RSET –0.0004 –0.4 –15 10 35 60 85 TEMPERATURE (°C) –0.0006 09128-011 –0.5 –40 0 0 –0.01 VLOOP = 24V 4mA TO 20mA RANGE RLOAD = 250Ω EXT NMOS EXT VREF , INT RSET EXT VREF , EXT RSET INT VREF , INT RSET INT VREF , EXT RSET 60 –0.05 –15 10 35 60 85 TEMPERATURE (°C) 0.0027 0.
PAGE 16
AD5421 Data Sheet 0.0005 COMPLIANCE VOLTAGE HEADROOM (V) 0.0010 0 –0.0005 –0.0010 –0.0015 –0.0020 0 10 20 30 40 50 60 LOOP SUPPLY VOLTAGE (V) 4.55 4.50 4.45 4.40 0 20 40 60 80 100 Figure 22. Compliance Voltage Headroom vs. Temperature 7 0.0030 VLOOP = 24V EXT NMOS RLOAD = 250Ω TA = 25°C ILOOP = 20mA 6 LOOP CURRENT ERROR (µA) 0.0025 0.0020 0.0015 0.0010 RLOAD = 250Ω TA = 25°C 3.
PAGE 17
AD5421 0.244 1.0 VLOOP = 24V ILOOP = 4mA 1.33mV p-p EXT NMOS RLOAD = 500Ω 0.2mV rms INT VREF TA = 25°C 0.8 0.6 IODVDD CURRENT (µA) 0.240 0.4 0.2 0 –0.2 –0.4 0.236 0.234 0.232 INCREASING 0.228 –0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.0 0.9 TIME (Seconds) 0.226 1.5 1.0 0.5 0 09128-027 0 2.0 DIGITAL LOGIC VOLTAGE (V) Figure 25. Loop Current Noise, 500 Hz to 10 kHz Bandwidth (HART Bandwidth) Figure 28. IODVDD Current vs. Digital Logic Voltage, Increasing and Decreasing, IODVDD = 1.
PAGE 18
AD5421 –15 1.82 –20 1.81 –25 1.80 –30 1.79 –35 1.78 –40 1.77 –45 3.0 0 2 4 6 8 10 –100 2.0 1.5 –150 1.0 –200 0.5 VLOOP = 24V EXT NMOS TA = 25°C 0 –250 1 0 –50 1.76 –50 2.5 2 12 REGOUT LOAD CURRENT (mA) 3 4 5 DVDD LOAD CURRENT (mA) 09128-030 REGOUT VOLTAGE (V) 1.83 DVDD OUTPUT VOLTAGE CHANGE (mV) 1.84 09128-101 0.25 0 VLOOP = 24V –5 EXT NMOS TA = 25°C –10 1.85 0 3.5 REGOUT LOAD CURRENT (mA) 0.10 0.15 0.20 DVDD OUTPUT VOLTAGE (V) 0.
PAGE 19
Data Sheet AD5421 2.5012 250 60 DEVICES SHOWN VLOOP = 24V EXT NMOS RLOAD = 250Ω ILOOP = 3.2mA 2.5010 200 ADC CODE (Decimal) REFOUT1 VOLTAGE (V) 2.5008 2.5006 2.5004 2.5002 2.5000 2.4998 150 100 50 –20 0 20 40 60 80 0 –40 09128-036 2.4994 –40 100 TEMPERATURE (°C) 20 40 60 80 100 Figure 39. On-Chip ADC Code vs. Die Temperature 250 30 VLOOP = 24V EXT NMOS TA = 25°C MEAN TC = 1.
PAGE 20
AD5421 Data Sheet TERMINOLOGY Total Unadjusted Error Total unadjusted error (TUE) is a measure of the total output error. TUE consists of INL error, offset error, gain error, and output drift over temperature, in the case of maximum TUE. TUE is expressed in % FSR.
PAGE 21
Data Sheet AD5421 THEORY OF OPERATION The AD5421 is an integrated device designed for use in looppowered, 4 mA to 20 mA smart transmitter applications. In a single chip, the AD5421 provides a 16-bit DAC and current amplifier for digital control of the loop current, a voltage regulator to power the entire transmitter, a voltage reference, fault alert functions, a flexible SPI-compatible serial interface, gain and offset adjust registers, as well as other features and functions.
PAGE 22
AD5421 Data Sheet Loop Voltage Fault LOOP CURRENT RANGE SELECTION There are two loop voltage alert bits in the fault register: VLOOP 12V and VLOOP 6V. If the voltage between the VLOOP and COM pins falls below 0.6 V (corresponding to a 12 V loop supply value), the VLOOP 12V bit is set; this bit is cleared when the voltage returns above 0.7 V. Similarly, if the voltage between the VLOOP and COM pins falls below 0.
PAGE 23
Data Sheet AD5421 Because the FAULT pin can go high for as long as 30 μs, care is required when performing a die temperature measurement after a readback of the VLOOP voltage. When switching from a VLOOP measurement to a die temperature measurement, the FAULT pin should not be read within 30 μs of switching, as a false trigger may occur (fault register contents are unaffected).
PAGE 24
AD5421 Data Sheet POWER-ON DEFAULT The AD5421 powers on with all registers loaded with their default values and with the loop current in the alarm state set to 3.2 mA or 22.8 mA/24 mA (depending on the state of the ALARM_ CURRENT_DIRECTION pin and the selected range). The AD5421 remains in this state until it is programmed with new values. The SPI watchdog timer is enabled by default with a timeout period of 1 sec.
PAGE 25
Data Sheet AD5421 10 100 8 50 6 0 4 –50 2 –100 0 –50 –150 –30 –10 10 TIME (ms) 30 50 Figure 48. Digitally Controlled Full-Scale Step and Resulting HART Digital Filter Output Signal Rev. G | Page 25 of 36 REGIN AD5421 VLOOP RL LOOP– CIN 168nF COM 47nF FROM HART MODEM Figure 49. Circuit Diagram for Figure 48 09128-061 150 OUTPUT OF HART DIGITAL FILTER (mV) HCF_TOOL-31 12 Figure 49 shows the circuit diagram for this measurement.
PAGE 26
AD5421 Data Sheet SERIAL INTERFACE The AD5421 is controlled by a versatile, 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2 shows the timing diagram. The interface operates with either a continuous or noncontinuous gated burst clock.
PAGE 27
Data Sheet AD5421 DAC REGISTER For the 3.8 mA to 21 mA output range, the loop current can be expressed as follows: The DAC register is a read/write register and is addressed as described in Table 12. The data programmed to the DAC register determines the loop current, as shown in the Ideal Output Transfer Function section and in Table 16.  17.2 mA  I LOOP =   × D + 3.8 mA 16  2  For the 3.
PAGE 28
AD5421 Data Sheet CONTROL REGISTER The control register is a read/write register and is addressed as described in Table 12. The data programmed to the control register determines the mode of operation of the AD5421. Table 17.
PAGE 29
Data Sheet AD5421 FAULT REGISTER The read-only fault register is addressed as described in Table 12. The bits in the fault register indicate a range of possible fault conditions. Table 19. Fault Register Bit Map MSB D15 SPI D14 PEC D13 ILOOP Over D12 ILOOP Under D11 Temp 140°C D10 Temp 100°C D9 VLOOP 6V D8 VLOOP 12V D7 D6 D5 D4 D3 D2 VLOOP/temperature value D1 LSB D0 Table 20.
PAGE 30
AD5421 Data Sheet OFFSET ADJUST REGISTER The offset adjust register is a read/write register and is addressed as described in Table 12. Table 21. Offset Adjust Register Bit Map MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 16-bit offset adjust data D5 D4 D3 D2 D1 LSB D0 D3 D2 D1 LSB D0 Table 22.
PAGE 31
Data Sheet AD5421 Transfer Function Equations with Offset and Gain Adjust Values For the 3.2 mA to 24 mA output range, the loop current can be expressed as follows: When the offset adjust and gain adjust register values are taken into account, the transfer equations can be expressed as follows. I LOOP For the 4 mA to 20 mA output range, the loop current can be expressed as follows: I LOOP    16 mA     16  × Gain 2   =  × D   216       20.8 mA   +  3.
PAGE 32
AD5421 Data Sheet APPLICATIONS INFORMATION negative with respect to COM. If it is possible that the voltage at LOOP− may be forced positive with respect to COM, or if the voltage difference between LOOP− and COM may be forced in excess of 5 V, a 4.7 V low leakage Zener diode should be placed between COM and the LOOP− pin, as shown in Figure 50, to protect the AD5421 from potential damage. Figure 50 shows a typical connection diagram for the AD5421 configured in a HART capable smart transmitter.
PAGE 33
Data Sheet AD5421 3.3V ADuCM360 AD5421 VDD PRESSURE SENSOR SIMULATION ADC 0 3.3V REGIN V-REGULATOR MICROCONTROLLER + VLOOP SRAM FLASH CLOCK RESET WATCHDOG LEXC TEMPERATURE SENSOR PT100 ADC TEMPERATURE SENSOR SPI COM ADC 1 DAC COM 52Ω WATCHDOG TIMER TEST CONNECTOR UART T1: CD T2: RTS T3: COM CIN LOOP– – T4: TEST VCC AD5700 HART_OUT 3.3V C_HART C_SLEW REF HART MODEM ADC_IP HART INPUT FILTER 09128-200 AGND DGND Figure 51.
PAGE 34
AD5421 Data Sheet Excessive junction temperature can occur if the AD5421 experiences elevated voltages across its terminals while regulating the loop current at a high value. The resulting junction temperature depends on the ambient temperature. To determine the absolute worst-case overall error, the reference and RSET errors can be directly summed with the specified AD5421 maximum error. For example, when using an external reference and external RSET resistor, the maximum AD5421 error is 0.
PAGE 35
Data Sheet AD5421 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 1 24 0.50 BSC 8 16 0.50 0.40 0.30 0.80 0.75 0.70 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 04-02-2012-A PIN 1 INDICATOR 0.30 0.25 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 54.
PAGE 36
AD5421 Data Sheet ORDERING GUIDE Model 1 AD5421ACPZ-REEL7 AD5421BCPZ-REEL7 AD5421BREZ AD5421BREZ-REEL AD5421BREZ-REEL7 AD5421CREZ AD5421CREZ-RL AD5421CREZ-RL7 EVAL-AD5421SDZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 32-Lead LFCSP_WQ 32-Lead LFCSP_WQ 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP 28-Lead TSSOP_EP Evaluation Board Z = RoHS Com